Multi-layered interconnect structure using liquid crystalline polymer dielectric

ABSTRACT

A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

RELATED APPLICATIONS

This application is a divisional application of Ser. No. 11/873,435,filed Oct. 11, 2007, which was a divisional application of Ser. No.10/959,711, filed Oct. 5, 2004, which was a divisional application ofSer. No. 10/263,849, filed Oct. 3, 2002, which was acontinuation-in-part of copending U.S. patent application Ser. No.10/067,551, filed Feb. 5, 2002 and entitled “Electronic Package ForElectronic Components and Method of Making Same.”

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates, in general, to a multi-layeredinterconnect structure, and in particular, to the lamination of liquidcrystal polymer (LCP) dielectric layers within the multi-layeredinterconnect structure.

2. Related Art

Organic substrates, such as chip carriers, have been and continue to bedeveloped for many applications. However, it would be desirable toreduce costs and inefficiencies that currently characterize fabricationof organic substrates.

SUMMARY OF THE INVENTION

In first embodiments, the present invention provides a multi-layeredinterconnect structure, comprising:

a thermally conductive layer including first and second opposingsurfaces;

a first liquid crystal polymer (LCP) dielectric layer directly bonded tothe first opposing surface of the thermally conductive layer with noextrinsic adhesive material bonding the first LCP dielectric layer tothe thermally conductive layer;

a second LCP dielectric layer directly bonded to the second opposingsurface of the thermally conductive layer with no extrinsic adhesivematerial bonding the second LCP dielectric layer to the thermallyconductive layer;

a first electrically conductive layer within the first LCP dielectriclayer; and

a second electrically conductive layer within the first LCP dielectriclayer and positioned between the first electrically conductive layer andthe thermally conductive layer, wherein the second electricallyconductive layer comprises a first plurality of shielded signalconductors.

In second embodiments, the present invention provides a method of makinga multi-layered interconnect structure, comprising:

providing a thermally conductive layer including first and secondopposing surfaces;

positioning a first liquid crystal polymer (LCP) dielectric layer on thefirst opposing surface of the thermally conductive layer, wherein thefirst LCP dielectric layer comprises a first LCP dielectric material,and wherein the first LCP dielectric layer includes a first LCPdielectric sublayer positioned on the first opposing surface of thethermally conductive layer, a first plurality of shielded signalconductors positioned on the first LCP dielectric sublayer, a second LCPdielectric sublayer positioned on the first plurality of shielded signalconductors, a first electrically conductive layer positioned on thesecond LCP dielectric sublayer, and a third LCP dielectric sublayerpositioned on the first electrically conductive layer; and

positioning a second LCP dielectric layer on the second opposing surfaceof the thermally conductive layer; wherein the second LCP dielectriclayer comprises a second LCP dielectric material; and

subjecting the first and second LCP dielectric layers to a first andsecond temperature that are less than the nematic-to-isotropictransition temperature of the first and second LCP dielectric materials,respectively, for a dwell time and at an elevated pressure that issufficient to cause the first and second LCP dielectric materials toplastically deform and to cause: bonding of the first LCP dielectricsublayer to the thermally conductive layer without any extrinsicadhesive layer disposed between the first LCP dielectric sublayer andthe thermally conductive layer, and bonding of the second LCP dielectricsublayer to the thermally conductive layer without any extrinsicadhesive layer disposed between the second LCP dielectric sublayer andthe thermally conductive layer.

In third embodiments, the present invention provides an electricalstructure, comprising:

a first 2S1P substructure, comprising a first dielectric layer, a firstpower plane within the first dielectric layer, a top signal plane on atop surface of the first dielectric layer, a bottom signal plane on abottom surface of the first dielectric layer, and a first electricallyconductive via;

a second 2S1P substructure, comprising a second dielectric layer, asecond power plane within the second dielectric layer, a top signalplane on a top surface of the second dielectric layer, a bottom signalplane on a bottom surface of the second dielectric layer, and a secondelectrically conductive via; and

a joining layer having first and second opposing surfaces and anelectrically conductive plug therethrough, wherein the joining layercomprises a liquid crystal polymer (LCP) dielectric material, whereinthe first opposing surface of the joining layer is directly bonded tothe first dielectric layer of the first 2S1P substructure with noextrinsic adhesive material bonding the joining layer to the firstdielectric layer, wherein the second opposing surface of the joininglayer is directly bonded to the second dielectric layer of the second2S1P substructure with no extrinsic adhesive material bonding thejoining layer to the second dielectric layer, and wherein theelectrically conductive plug electrically couples the first electricallyconductive via to the second electrically conductive via.

In fourth embodiments, the present invention provides a method forforming an electrical structure, comprising:

providing a first 2S1P substructure, said first 2S1P substructurecomprising a first dielectric layer, a first power plane within thefirst dielectric layer, a top signal plane on a top surface of the firstdielectric layer, a bottom signal plane on a bottom surface of the firstdielectric layer, and a first electrically conductive via;

providing a second 2S1P substructure, said second 2S1P substructurecomprising a second dielectric layer, a second power plane within thesecond dielectric layer, a top signal plane on a top surface of thesecond dielectric layer, a bottom signal plane on a bottom surface ofthe second dielectric layer, and a second electrically conductive via;

providing a joining layer, said joining layer having first and secondopposing surfaces and an electrically conductive plug therethrough,wherein the joining layer comprises a liquid crystal polymer (LCP)dielectric material; and

directly bonding the joining layer to the first dielectric layer of thefirst 2S1P substructure at the first opposing surface and to the seconddielectric layer of the second 2S1P substructure at the second opposingsurface, by subjecting the first 2S1P substructure, the joining layer,and the second 2S1P substructure to an elevated temperature, elevatedpressure, and dwell time sufficient for effectuating said bonding,wherein the elevated temperature is less than the nematic temperature ofthe LCP dielectric material during the dwell time, wherein no extrinsicadhesive material is disposed between the joining layer and the firstdielectric layer, wherein no extrinsic adhesive material is disposedbetween the joining layer and the second dielectric layer, and whereinthe electrically conductive plug electrically couples the firstelectrically conductive via to the second electrically conductive via.

The present invention advantageously reduces processing time andprocessing costs, and reduces dielectric layer thickness, in thefabrication of organic substrates.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a front sectional view of an electronic package that includesa semiconductor chip assembled to a multi-layered interconnectstructure, and the multi-layered interconnect structure assembled to acircuitized substrate, in accordance with preferred embodiments of thepresent invention.

FIG. 2 is a process flow diagram showing a method for making theelectronic package of FIG. 1, in accordance with preferred embodimentsof the present invention.

FIG. 3 depicts a front cross-sectional view of a resin coated metalcomprising a dielectric resin having a modified polyphenylene ether(MPPE) on a metal foil, in accordance with preferred embodiments of thepresent invention.

FIG. 4 depicts a FIG. 3 with zoomed view of a metal foil surface thatinterfaces the MPPE.

FIG. 5 depicts a front cross-sectional view of a resin coated metalcomprising a dielectric resin having a MPPE on a metal foil.

FIG. 6 depicts an electronic configuration including: the resin coatedmetal of FIG. 3, the resin coated metal of FIG. 5, and a portion of themulti-layered interconnect structure of FIG. 1.

FIG. 7 depicts FIG. 6 after the electronic configuration has beenpressurized and after the metal foils of the resin coated metals haveremoved.

FIG. 8 depicts a localized molecular domain in the liquid crystal phaseof a liquid crystal polymer (LCP) dielectric, with directional orderingof polymer chains, in accordance with embodiments of the presentinvention.

FIG. 9 depicts a localized molecular domain in the isotropic phase of aLCP dielectric, with little or no directional ordering of polymerchains, in accordance with embodiments of the present invention.

FIGS. 10 and 11 illustrate flat-bed press lamination for lamination ofstacked layers that include LCP dielectric material, in accordance withembodiments of the present invention.

FIG. 12 illustrates an autoclave lamination press for lamination ofstacked layers that include LCP dielectric material, in accordance withembodiments of the present invention.

FIGS. 13-19 depict forming a 2S1P substructure, in accordance withembodiments of the present invention.

FIGS. 20-23 depict forming a joining layer for joining together two 2S1Psubstructures, in accordance with embodiments of the present invention.

FIGS. 24-25 depict joining two 2S1P substructures with a joining layer,in accordance with embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention concerns a multi-layered interconnect structurecomprising a dielectric material, and methodology for forming themulti-layered interconnect structure. This Detailed description sectionis divided into three subsections. The first subsection describes themulti-layered interconnect structure and methodology for its formationin terms of a first dielectric material embodiment (“First DielectricMaterial Embodiment”). The second subsection describes the multi-layeredinterconnect structure and methodology for its formation in terms of asecond dielectric material embodiment in which a liquid crystal polymer(LCP) dielectric is utilized (“Second Dielectric Material Embodiment”).The third subsection describes a particularized multi-layeredinterconnect structure in which a joining layer comprising LCPdielectric material is used to join together two other substructuressuch as 2S1P substructures (“Joining Layer Embodiment”).

First Dielectric Material Embodiment

The present invention provides an electronic package which includes amulti-layered interconnect structure (e.g., a substrate comprisingorganic dielectric material, such as an organic chip carrier) and asemiconductor chip, the multi-layered interconnect structure beingrelatively compliant and having a coefficient of thermal expansion (CTE)of about 10 to about 12 ppm/° C. which will not cause failure ofinterconnections between the semiconductor chip and a printed circuitboard to which the package can be assembled. The multi-layeredinterconnect structure may be comprised of a single layer as anembodiment of the present invention. Failure of an interconnection, suchas a solder interconnection, is defined as an increase of at least oneohm in electrical resistance of the interconnection as a consequence ofbeing subjected to each test (i.e., test category) of Thermal AcceptanceTesting (TAT), wherein the interconnection is actually tested under eachTAT test or is alternatively subjected to engineering calculation orcomputer simulations which determine, according to accepted engineeringstandards and methodology, whether the interconnection would experiencesaid increase of at least one ohm in electrical resistance if actuallysubjected to each TAT test. The electrical resistance of theinterconnection prior to TAT is used as a reference value forcalculating said increase in electrical resistance following any TATtest. Passing of an interconnection is defined as not failing. ThermalAcceptance Testing includes the following four test categories: anair-to-air test, a wet thermal shock test, a thermal cycle test, and apower cycle test.

The air-to-air test is the Joint Electron Device Engineering Council(JEDEC) test method A104-A, condition G, which includes immersion of theorganic substrate with an attached chip in air at −40 EC until both theorganic substrate and the attached chip are at −40 EC throughout(typically 10 minutes), followed by immersion in another bath of air at125 EC until both the organic substrate and the attached chip are at 125EC throughout (typically 10 minutes), for 1000 cycles.

The wet thermal shock test is the JEDEC test method A106-A, whichincludes immersion of the organic substrate with an attached chip in aliquid bath at −40 EC until both the organic substrate and the attachedchip are at −40 EC throughout (typically 10 minutes), followed byimmersion in another liquid bath at 125 EC until both the organicsubstrate and the attached chip are at 125 EC throughout (typically 10minutes), for 100 cycles.

The thermal cycle test cycles the whole assembly (organic substrate withattached chip and attached circuit card) in a chamber of air that cyclesthe air from 0 EC to 100 EC for 3600 cycles, wherein the extreme chambertemperatures of 0 EC and 100 EC are each maintained until the wholeassembly reaches a uniform steady-state temperature.

The power cycle test cycles the whole assembly (organic substrate withattached chip and attached circuit card) from 25 EC (i.e., ambient roomtemperature) to 125 EC, for 3600 cycles. During the heating phase, thechip is powered up and serves as the heat source for the whole assembly.The high-temperature end of a cycle occurs when the chip is at 125 ECwith a consequent temperature distribution across the entire assemblythat is intended to realistically simulate temperature distributionsthat would occur during actual field operation.

Referring to FIG. 1, a partial sectional view, in elevation, of oneembodiment of the electronic package 10 of the invention is shown. Theelectronic package 10 includes an electronic device, such as asemiconductor chip 12 having a first surface 14, the first surfaceincluding a plurality of contact members 16, thereon. The plurality ofcontact members 16 are preferably Controlled Collapse Chip Connection(C4) solder balls, each coupled to a respective contact (not shown) onthe chip's first surface 14. Other contact member shapes that can beused in this invention are columns and cylinders. C4 solder balls arecomprised of solder material preferably having a composition of about97% lead and about 3% tin with a melting point of about 310° C. Theelectronic package includes a multi-layered interconnect structure 18,preferably an organic chip carrier, adapted for electricallyinterconnecting the semiconductor chip 12 to an electronic device suchas a circuitized substrate 100 (e.g., a printed circuit board) by meansof a first plurality of solder connections, preferably solder balls suchas ball grid array (BGA) solder balls. The multi-layered interconnectstructure 18 (which will be described infra in detail) includes athermally conductive layer 22 having first and second opposing surfaces24 and 26, respectively. A first dielectric layer 28, which may includesublayers 29, 39, 30, 31 and 32, is positioned on the first opposingsurface 24. A second dielectric layer 34, which may include sublayers35, 41, 36, 37 and 38, is positioned on the second opposing surface 26.First dielectric layer 28 can also include first conductive layer 31,between the dielectric layers 30 and 32 for serving as power and/orground connections. Second dielectric layer 34 can also include thirdconductive layer 37, between the dielectric layers 36 and 38 for servingas power and/or ground connections. The first dielectric layer 28 andthe second dielectric layer 34 can further include second and fourthelectrically conductive layers 39 and 41, respectively. Electricallyconductive layers 39 and 41 are preferably signal carrying conductors.The second electrically conductive layer 39 is positioned between thefirst electrically conductive layer 31 and the thermally conductivelayer 22. The fourth electrically conductive layer 41 is positionedbetween the third electrically conductive layer 37 and the thermallyconductive layer 22. Electrically conductive layers 31, 37, 39, and 41can be comprised of a suitable metal such as copper or aluminum,(preferably copper) and can have a thickness of from about 0.20 to about1.0 mils, preferably about 0.50 mils. An aspect of the current inventionis that each of the signal carrying layers 39 and 41 is shielded oneither side by an electrically conducting layer which significantlyreduces signal noise. Signal carrying layer 39 is shielded byelectrically conducting layers 31 and 22, while signal carrying layer 41is shielded by electrically conducting layers 37 and 22.

As a first dielectric material embodiment of the present invention,layers 29, 30 and 32 of first dielectric layer 28, and layers 35, 36 and38 of second dielectric layer 34 may comprise an organic polymericmaterial which may be filled with a particulate material. The dielectricconstant of these dielectric layers is preferably from about 1.5 toabout 3.5, and more preferably from about 2 to about 3. The thickness ofthe filled dielectric layers can vary according to the desired designperformance characteristics of the multi-layered interconnect structure18, and said thicknesses may be about equal if so dictated by designperformance requirements. Significantly, the dielectric material of thedielectric layers 28 and 34 does not contain conventional wovenfiberglass. Such absence of woven fiberglass enables through holes to beclosely spaced. Indeed, spacing between through hole centers of lessthan 100 mils, preferably less than 50 mils but more preferably about 25mils and most preferably less than 10 mils, is achievable withoutelectrical shorting between adjacent conductive through holes.Preferably, the particulate filler has a diameter less than about 10 Φm,more preferably from about 5 to about 8 Φm. Preferably, the particulatefiller is present from about 30 to about 70 percent by weight, morepreferably from about 40 to about 60 percent by weight of the material.Preferably, the particulate filler is silica. Suitable materials for thedielectric layer include, for example, cyanate ester andpolytetrafluoroethylene. A suitable silica filledpolytetrafluoroethylene is available as HT 2800 from Rogers Corporation(Rogers, Conn.).

A first plurality of electrically conductive members 40 is positioned onthe first dielectric layer 28 and a second plurality of electricallyconductive members 42 is positioned on the second dielectric layer 34.These electrically conductive members 40 and 42 may comprise a metalsuch as, inter alia, copper. The first and second pluralities ofelectrically conductive members 40 and 42 can each have thicknessesranging from about 0.25 to about 1.5 mils. A first plurality of solderconnections 47 positioned on a first plurality of microvias 55 and inelectrical contact with the first plurality of electrically conductivemembers 40 are electrically connected to respective ones of theplurality of contact members 16 on the semiconductor chip 12. The firstplurality of microvias 55 are a first plurality of openings withinternal walls formed in a third dielectric layer 46 that expose atleast portions of the first plurality of electrically conductive members40. Each of the first plurality of openings includes a layer ofelectrically conductive material 45 (e.g., copper), positioned on theinternal walls of the first plurality of openings and on portions ofselected ones of the plurality of first electrically conductive members40. The first plurality of solder connections 47 are comprised of a lowmelt solder (melting temperature below about 230° C.), such as interalia eutectic solder, comprised of a composition of about 63% lead andabout 37% tin.

The thermally conductive layer 22 is comprised of a material having aselected thickness and coefficient of thermal expansion to substantiallyprevent failure of the first plurality of solder connections 47 betweenthe first plurality of electrically conductive members 40 andsemiconductor chip 12. Thermally conductive member (or layer) 22 can bea suitable metal comprised of nickel, copper, molybdenum, or iron. Thethermally conductive layer 22 may function as a ground plane. Anembodiment of thermally conductive layer 22 (which has a CTE of close tozero such as, inter alia, between about 4 ppm/° C. and about 8 ppm/° C.)is a three layered structure comprised of a first layer of copper, asecond layer of an alloy of about 34% to about 38% nickel (e.g., about36% nickel) and about 62% to about 66% iron (e.g., about 63% iron), anda third layer of copper. The overall CTE (i.e., spatially averaged CTE)of thermally conductive layer 22 is from about 4 to about 8 ppm/° C.About 72% to about 80% of the thickness of the thermally conductivelayer 22 may be the nickel-iron alloy and about 20% to about 28% of thethickness of the thermally conductive layer may be copper. A suitable36% nickel-63% iron alloy is available from Texas InstrumentsIncorporated (Attleboro, Mass.). Alternatively, the thermally conductivelayer 22 can be formed solely of a single metal alloy such as a about36% nickel-about 63% iron alloy. The thickness of the thermallyconductive layer 22 may be from about 1 mil to about 3 mils. Thethickness and choice of material for the thermally conductive layer 22will determine the CTE of the thermally conductive layer 22 and,significantly, can be used to control the overall CTE of themulti-layered interconnect structure 18 when used in combination withthe other elements defined herein. When the CTE is about 10 to about 25ppm/° C., a significant advantage is achieved. Strain control on thefirst plurality of solder connections 47 of the electronic package 10 isrealized and localized regions of high strain are avoided duringoperation of the electronic package 10 (when assembled to a circuitizedsubstrate and in field operation). The overall strain between thesemiconductor chip 12, with a CTE of about 2-3 ppm/° C., and thecircuitized substrate 100, with a CTE of about 17-20 ppm/° C., is thussignificantly reduced in magnitude. To prevent failure ofinterconnections within the multi-layered interconnect structure 18,between the multi-layered interconnect structure 18 and thesemiconductor chip 12, and between the circuitized substrate 100 and themulti-layered interconnect structure 18, the difference between theoverall CTE of the multi-layered interconnect structure 18 and the CTEof the semiconductor chip 12 should be between about 40% and about 70%(but preferably between about 40% and about 60%) of the differencebetween the CTE of the circuitized substrate 100 and the CTE of thesemiconductor chip 12. For controlling the CTE of the multi-layeredinterconnect structure 18 to prevent failure of the aforementionedinterconnections, it is noted that the overall CTE of the multi-layeredinterconnect structure 18 depends on both the CTE and thickness of thethermally conductive layer 22. It is accordingly preferred that the CTEof the thermally conductive layer 22 be between about one third andabout two thirds (depending on the thickness of the thermally conductivelayer 22) of the overall CTE of the multi-layered interconnect structure18.

With the first dielectric embodiment of the present invention, describedsupra, layers 29, 30, 32 of first dielectric layer 28 and layers 35, 36,and 38 of second dielectric layer 34 may comprise a filled organicpolymeric material having an effective modulus from about 0.01 to about0.50 Million pounds per square inch (Mpsi), and preferably the effectivemodulus is from about 0.03 to about 0.10 Mpsi. The dielectric materialof layers 29, 30, 32, 35, 36, and 38 includes material which can deformin an elastic manner under stress, and if subjected to sufficient stresscan deform in an elastic-plastic manner. The effective modulus isdefined as a secant modulus which in turn is defined as a relation ofthe tensile stress to total strain of an elastic-plastic stress-strainmaterial test stress response curve (see, for example, A. Blake,“Practical Stress Analysis in Engineering Design”, Marcel Dekker: 270Madison Ave., New York, N.Y. 10016, 1982.) It is useful to employ adielectric material having a measured tensile secant modulus within therange of 0.01 to 0.5 Mpsi, measured at room temperature, with a strainrate between the values of 0.01/min and 0.6/min, with the test conductedat a temperature between 10 and 30° C. When the first and seconddielectric layers 28 and 34, respectively, are comprised of a materialwith this effective modulus, the multi-layered interconnect structure isrelatively compliant, and warpage during operation of the electronicpackage is greatly reduced. This unique combination of the reduced CTEthermally conductive layer and the compliant (during operation)dielectric layers assures the prevention of failure of the firstplurality of solder connections 47 between the semiconductor chip 12 andmulti-layered interconnect structure 18, and between structuremulti-layered interconnect 18 and the circuitized substrate 100. As aresult, semiconductor chip 12 will experience much less warpage thanwould occur with laminates made of typical organic materials.Multi-layered interconnect structure 18 is capable of absorbing a modestamount of internal shear strain under the die. If an encapsulant isapplied between the semiconductor chip 12 and the multi-layeredinterconnect structure 18, the compliancy of the structure will resultin significantly less stress within the encapsulant. The combination ofthe strain control on the first plurality of solder connections 47 andthe reduced tendency for the electronic package 10 to warp bothcontribute to preventing failure of the first plurality of solderconnections 47 between the first plurality of electrical conductivemembers 40 and semiconductor chip 12.

A first plated through hole 50 (i.e., a first through hole plated with ametal, preferably copper) is positioned under semiconductor chip 12 andis electrically connected to at least one electrically conductive memberof the first plurality of electrically conductive members 40 and to atleast one electrically conductive member of the second plurality ofelectrically conductive members 42. The first plated through hole 50 isalso electrically connected to at least one of the first plurality ofshielded signal conductors which comprise conductive layer 39. A secondplated through hole 52 (i.e., a second through hole plated with a metalsuch as inter alia copper) is positioned under semiconductor chip 12 andis also electrically connected to at least one electrically conductivemember of the first plurality of electrically conductive members 40 andto at least one electrically conductive member of the second pluralityof electrically conductive members 42. Although not explicitly shown inFIG. 1, the second plated through hole 52 is also electrically connectedto at least one of the second plurality of shielded signal conductorswhich comprise conductive layer 41. First and second plated throughholes 50 and 52, respectively, have an unplated diameter from about 1.5to about 3.0 mils and can be formed by mechanical or laser drilling,preferably by laser drilling with a commercial YAG or excimer laser. Theplated through holes 50 and 52 each include a layer of about 0.15 toabout 1.0 mils of a suitable plated metal (e.g., copper) on internalwalls of the through holes 50 and 52. As an embodiment each contact siteof the semiconductor chip is electrically connected to no more than oneplated through hole of the multi-layered interconnect structure 18.

The third dielectric layer 46 of the multi-layered interconnectstructure 18 is positioned on the first dielectric layer 28 and on atleast a portion of selected ones of the first plurality of electricallyconductive members 40. The third dielectric layer 46 can substantiallycover (i.e., tent) the first and second plated through holes 50 and 52,respectively. The fourth dielectric layer 48 is positioned on the seconddielectric layer 34 and on at least a portion of selected ones of thesecond plurality of electrically conductive members 42. The fourthdielectric layer 48 of the multi-layered interconnect structure 18 cansubstantially cover (i.e., tent) the first and second plated throughholes 50 and 52, respectively. The third and fourth dielectric materialand fourth dielectric material may substantially fill the plated throughholes 50 and 52, respectively, as shown. Alternatively, the platedthrough holes 50 and 52 may be filled with a material other than thethird and fourth dielectric material prior to positioning the thirddielectric layer 46 and the fourth dielectric layer 48 on the firstdielectric layer 28 and the second dielectric layer 34, respectively.

Dielectric material of the third dielectric layer 46 (“third dielectricmaterial”) and of the fourth dielectric layer 48 (“fourth dielectricmaterial”) can be a suitable organic polymeric material. A preferredthird and fourth dielectric material is a resin comprising a modifiedpolyphenylene ether (MPPE). Useful MPPE resins which may be used inconjunction use with the present invention are disclosed in U.S. Pat.No. 5,352,745 (Katayose et al. issued Oct. 4, 1994) (“Katayose '745”),assigned to Asahi Kasei Kogyo Kabushiki Kaisha of Tokyo, Japan, andincorporated herein by reference in its entirety. The MPPE resin isdescribed in the Katayose '745 patent as a curable polyphenylene etherresin composition comprising a reaction product obtained by reacting apolyphenylene ether with an unsaturated carboxylic acid or an acidanhydride and at least one cyanurate. Useful MPPE resins which may beused in conjunction use with the present invention are disclosed in U.S.Pat. No. 5,218,030 (Katayose et al. issued Jun. 8, 1993) (“Katayose'030”), assigned to Asahi Kasei Kogyo Kabushiki Kaisha of Tokyo, Japan,and incorporated herein by reference in its entirety. In relation toMPPE resins, the Katayose '030 patent describes the use ofpoly(phenylene ether) containing pendant allyl or propargyl groups,triallylcyanurate or triallylisocyanurate, and optionally anantimony-containing flame retardant; other formulations replace theantimony flame retardant with bromine containing compounds. Useful MPPEresins which may be used in conjunction use with the present inventionare disclosed in U.S. Pat. No. 6,352,782 B2 (Yeager et al. issued Mar.5, 2002) (“Yeager '782”), assigned to General Electric Company, andincorporated herein by reference in its entirety. The modified PPE resinas described in the Yeager '782 patent is a reactively end cappedpoly(phenylene ether) compound cured with certain unsaturated compounds.

The MPPE material may be utilized in the form of the MPPE resin coatedonto a metal foil, such as a copper foil. A commercially availablemodified MPPE that is suitable for the present invention is manufacturedby the Asahi Chemical Company of Japan and is identified as Asahiproduct number PC5103, which comprises the resin coated onto a copperfoil. The MPPE material is particularly suitable for the third andfourth dielectric material of the present invention, because the MPPEmaterial retains its structural integrity, and does not crack, whensubjected to Thermal Acceptance Testing, described supra.

Several factors help explain why the MPPE material is useful for thepresent invention. A first factor is that if the allyl group is used,then the allyl group of the MPPE can form cross links and thus addhardness and stiffness to the polyphenylene ether polymer. A secondfactor is that the Asahi MPPE has a CTE that material that issubstantially below the CTE of other organic polymers. The lower CTE ofthe MPPE material improves thermal compatibility of the third layer 46and the fourth layer 48 with the remaining multi-layered interconnectstructure which may have a CTE of about 10 to about 12 ppm/° C. Amismatch between the CTE of the third and fourth dielectric materialsand the lower CTE of other structural components of the electronicpackage 10 is considered to be a significant factor in determiningwhether the third and fourth dielectric materials will retain itsstructural integrity and resist cracking. Another beneficialcharacteristic that may be comprised by a MPPE material is an absence ofvolatile solvents capable of vaporizing while being laminated (e.g., byvacuum lamination) to the first dielectric layer 28 or the seconddielectric layer 34, wherein such vaporization would cause shrinkage ofthe redistribution layer.

Third dielectric layer 46 includes the first plurality of microvias 55.The first plurality of microvias 55 constitute a first plurality ofopenings defined by internal walls formed in third dielectric layer 46,said openings exposing portions of selected ones of the first pluralityof electrically conductive members 40. Each of the first plurality ofopenings includes a layer of electrically conductive material 45positioned on the internal walls of the first openings and, preferably,also on the exposed portions of the first plurality of electricallyconductive members 40. Generally, a microvia that includes a layer ofelectrically conductive material positioned on its internal walls isdesignated as a “plated blind via.” Selected ones of the first pluralityof microvias 55 (or plated blind vias 55) are electrically (i.e.,conductively) coupled to respective ones of the first plurality ofsolder connections 47, and thus electrically coupled to the firstplurality of electrically conductive members 40. One plated blind via,in addition to the first plurality of microvias 55, is within the scopeof the present invention and, accordingly, at least one plated blind via(such as one of plated blind vias 55) may be conductively coupled to oneof the first plurality of electrically conductive members 40. The firstplurality of solder connections 47 are designed to efficiently match thepattern of contact members 16 on semiconductor chip 12. Preferably,there is a match of no more than one contact member 16 with one of theplated through holes 50 or 52 under the semiconductor chip providing adirect electrical path from each of the contact members 16 to either thesignal carrying second electrical conductive layer 39 (through one ofthe solder connections 47, one of the first electrically conductivemembers 40, and plated through hole 50) or to the signal carrying fourthelectrically conductive layer 41 (through one of the solder connections47, another first electrically conductive member 40, and through platedthrough hole 52). Thus the third dielectric layer 46 comprises a highdensity interconnect layer for providing a direct electrical path from acontact member 16 to a shielded signal conductor, which provides arelatively short and efficient electrical path for signals to betransmitted from the semiconductor chip 12 through the multi-layeredinterconnect structure 18. Similarly, the fourth dielectric layer 48comprises a high density interconnect layer for providing a directelectrical path from the multi-layered interconnect structure 18 to thecircuitized substrate 100 through the second plurality of solderconnections 20.

The fourth dielectric layer 48 includes a second plurality of microvias54. The second plurality of microvias 54 are a second plurality ofopenings with internal walls formed in the fourth dielectric layer thatexpose portions of electrically conductive members 42. Each of thesecond plurality of openings 54 includes a layer of electricallyconductive material positioned on the internal walls of the openings andon the exposed portions of the second plurality of electricallyconductive members 42 to form a plurality of conductive bonding pads 56.The conductive material on the internal walls of the first and secondpluralities of openings and on the exposed portions of the first andsecond pluralities of electrically conductive members 40 and 42 in thethird and fourth dielectric layers is preferably plated copper. As shownin FIG. 1, the semiconductor chip 12 is conductively coupled to thefirst plurality of microvias 55 by the plurality of contact members 16(e.g., C4 solder balls). Generally, any electronic device (e.g., asemiconductor chip such as the semiconductor chip 12) may beconductively coupled to a microvia of the first plurality of microvias55. Further, one microvia (or plated blind via), in addition to thefirst plurality of microvias 55, in the third dielectric material 46 iswithin the scope of the present invention.

The electronic package can further include a circuitized substrate 100having a plurality of contact pads 103 on a first surface 104, whichpads are electrically connected to respective ones of second pluralityof solder connections 20 (e.g., solder balls) on multi-layeredinterconnect structure 18. Typically, the second plurality of solderconnections 20 are arranged as solder balls in a ball grid array (BGA)arrangement to efficiently allow electrical signal transmission andpower distribution out of and into the electronic package. The secondplurality of solder connections 20 can also be comprised of columns orother shapes to provide the appropriate stand off and appropriate strainrelief between multi-layered interconnect structure 18 and circuitizedsubstrate 100. Typically the solder balls are comprised of a low meltsolder metallurgy, preferably a eutectic solder material. As shown inFIG. 1, the circuitized substrate 100 is conductively coupled to thesecond plurality of microvias 54 by the second plurality of solderconnections 20 (e.g., BGA solder balls). Generally, any electronicdevice (e.g., a circuitized substrate such as the circuitized substrate100) may be conductively coupled, by one of the second plurality ofsolder connections 20 on one of the conductive bonding pads 56, to amicrovia of the second plurality of microvias 54. Further, one microvia(or plated blind via), in addition to the second plurality of microvias54, in the fourth dielectric material 48 is within the scope of thepresent invention.

The multi-layered interconnect structure 18 has an overall CTE thatprevents failure of: the first solder connections 47, the second solderconnections 20, and interconnections within the multi-layeredinterconnect structure 18. The difference between the overall CTE of themulti-layered interconnect structure 18 and the CTE of the semiconductorchip 12 is preferably between about 40% and about 60% of the differencebetween the CTE of the circuitized substrate 100 and the CTE of thesemiconductor chip 12. The thermally conductive layer 22 has a thicknessand CTE to prevent failure of: the solder connections 47, the solderconnections 20, and interconnections within the multi-layeredinterconnect structure 18. In particular, the thermally conductive layer22 has a CTE that is between about one third and about two thirds of theCTE of overall CTE of the multi-layered interconnect structure 18.

Although not shown in FIG. 1, a stiffener ring for mechanicallystabilizing the multi-layered interconnect structure 18 may beadhesively bonded to an outer portion of a top surface 44 of themulti-layered interconnect structure 18, such as to an outer perimeterportion. An organic chip carrier, such as the multi-layered interconnectstructure 18, that is made of such compliant organic material (e.g., amaterial having a modulus of less than 300,000 psi) cannot be easilyhandled. The stiffener ring, which is rigid, enhances the structuralcharacteristics of the chip carrier (i.e., the multi-layeredinterconnect structure 18) by making the chip carrier more mechanicallystable and thus easier to handle.

Referring to FIG. 2, a method 60 of making the multi-layeredinterconnect structure 18 of FIG. 1 is shown. The resultingmulti-layered interconnect structure 18, as defined herein, is adaptedfor electrically interconnecting the semiconductor chip 12 and thecircuitized substrate 100 using solder connections. The first step 62 inthis method is providing a thermally conductive layer 22 having firstand second opposing surfaces 24 and 26. The multi-layer interconnectstructure has been previously described supra in detail and includes athermally conductive layer material having a selected thickness andcoefficient of thermal expansion.

Next, step 64 includes positioning first and second dielectric layers 28and 34 on the first and second opposing surfaces 24 and 26,respectively, of the thermally conductive layer 22. Step 64 is performedby laminating copper clad, silica filled PTFE layers in a laminatingpress at a pressure of about 1000 to about 2000 pounds per square inch(psi.) and at a temperature of about 600 to about 750 degrees Fahrenheit(° F.) to the first and second opposing surfaces of the thermallyconductive layer. However, performing the aforementioned lamination offirst and second dielectric layers 28 and 34 (i.e., silica filled PTFE)to the first and second opposing surfaces of the thermally conductivelayer, respectively, at a lamination temperature between about 670 andabout 695 degrees Fahrenheit (° F.) advantageously results in improvedductility (i.e., higher ductility) of the first and second dielectriclayers 28 and 34, as is described in currently pending patentapplication entitled “Electronic Package With Optimized LaminationProcess,” (Farquhar et al.; filed Sep. 24, 2002; application Ser. No.10/253,725; U.S. Patent Application Publication No. 2003/0020156 A1;Certificate of Mailing by Express Mail label number EK953785282US), andincorporated herein by reference in its entirety.

Step 66 includes forming the plurality of through holes 50 and 52 in themulti-layered interconnect structure 18 by laser drilling with a YAG orexcimer laser. Other suitable means of drilling are possible, such asmechanical drilling. The through holes 50 and 52 formed are from about0.5 to about 2.0 mils in diameter. The holes 50 and 52, and the internalwalls of the holes 50 and 52, are then cleaned in preparation for theaddition of a conductive layer. The copper cladding on the first andsecond dielectric layers 28 and 34 and the internal walls of theplurality of through holes 50 and 52 are then electrolessly seeded andplated with a continuous layer of a metal. The walls are plated with athickness of metal from about 0.1 to about 1.0 mils. Suitable metals arecopper and aluminum, with copper being the preferred metal.

Step 68 illustrates positioning first and second pluralities ofelectrically conductive members 40 and 42 on the first and seconddielectric layers 28 and 34, respectively, by any method known to one ofordinary skill in the art. For example, a photoresist may be applied onthe surfaces of the plated copper clad dielectric layers. Thephotoresist tents the plurality of plated through holes 50 and 52 toprotect the plated internal walls of the plated through holes 50 and 52from subsequent etching steps. The photoresist is then exposed anddeveloped. A pattern of first and second pluralities of electricallyconductive members 40 and 42 is then formed by etching the exposedportions of the plated metal and the copper cladding on the surface ofthe first and second dielectric layers 28 and 34, respectively, with acupric etch. The photoresist is then stripped with a caustic stripper,such as sodium hydroxide, resulting in first and second pluralities ofelectrically conductive metal members 40 and 42 on the surfaces of thefirst and second dielectric layers 28 and 34, respectively. The firstplurality of electrically conductive members 40 are preferably formed assubstantially dog bone shaped segments. Each segment includes at leasttwo metal pads; one end of the substantially dog bone shaped segment,the first metal pad, being connected to the metal plating on theinternal walls of one of the plurality of plated through holes 50 or 52at the surface of the first dielectric layer 28 and the other end of thesubstantially dogbone shaped segment being a second metal pad adaptedfor having a solder connection thereon and being electrically connectedto the semiconductor chip 12. The first and second metal pads of eachsubstantially dogbone-shaped segment are preferably connected by asubstantially straight conductor segment. The second plurality ofelectrically conductive members 42 are also formed of substantiallydogbone shaped segments, each segment including at least two metal pads;one end of the substantially dogbone shaped segment, the third metalpad, being connected to the metal plating on the walls of one of theplurality of plated through holes 50 or 52 at the surface of the seconddielectric layer 34 and the other end of the substantially dogboneshaped segment being a fourth metal pad adapted for having a solderconnection thereon for connecting to circuitized substrate 100. Thesolder connection can be a solder ball, solder column, or a land. Thirdand fourth metal pads of the substantially dogbone shaped segments arealso connected by a substantially straight conductor segment. Eventhough substantially dogbone shaped segments may be as described herein,many other pad shapes are possible.

Step 70 includes positioning the third dielectric layer 46 on thesublayer 32 of the first dielectric layer 28 and on the first pluralityof electrically conductive members 40, and the fourth dielectric layer48 on the sublayer 38 of the second dielectric layer 34 and on thesecond plurality of electrically conductive members 42. FIGS. 3-5illustrate the dielectric material of the third and fourth dielectriclayers 46 and 48, respectively, said dielectric material including thepreferred dielectric resin having a modified polyphenylene ether (MPPE).FIG. 3 illustrates a front cross-sectional view of a resin coated metal80 comprising a dielectric resin 82 having a modified polyphenyleneether (MPPE), said resin 82 adhesively coupled to a metal foil 83 (e.g.,a copper foil). As an example of the resin coated metal 80, the AsahiPC5103 material mentioned supra comprises the MPPE resin coated on acopper foil. Inasmuch as the uncured resin 82 has mechanical propertiesthat make it difficult to handle, the mechanical structure of the metalfoil 83 compensates for the difficult-to-handle mechanical structure ofthe resin 82. The resin 82 has a thickness preferably between about 30microns and about 70 microns. The metal foil 83 preferably has athickness of at least about 9 microns. The metal foil 83 is rough in thesense of having peaks and valleys on the surface 84 of the metal foil83, said surface 84 mechanically interfacing with the resin 82. FIG. 4includes the surface 85 as a zoomed (i.e., blown up) view of the surface84 of FIG. 3 showing the peaks and valleys. Noting that the metal foil83 will be later removed, such as by etching, the roughness of thesurface 84 (or 85) of the metal foil 83 will leave a surface impressionon the resin 82 after the metal foil 83, is subsequently removed. Saidsurface impression is “complementary” to the metal roughness structureof the surface 84 (or 85); i.e., the resultant valleys and peaks in theresin 82 surface after the metal foil 83 is removed corresponds to thepeaks and valleys, respectively, of the metal roughness structure 84 (or85) that existed while the metal foil 83 was mechanically interfacedwith the resin 82. The resin coated metal 80 will subsequently betransformed into the third dielectric layer 46 of FIG. 1.

FIG. 5 illustrates a front cross-sectional view of a resin coated metal90 comprising a dielectric resin 92 having a modified polyphenyleneether (MPPE), said resin 92 adhesively coupled to a metal foil 93. Theresin coated metal 90 has all of the characteristics that was discussedsupra for the resin coated metal 80 of FIGS. 3 and 4, including asurface 94 of the metal foil 93 that is rough in the same manner thatthe surface 84 of the metal foil 83 is rough. The resin coated metal 90of FIG. 5 will subsequently be transformed into the fourth dielectriclayer 48 of FIG. 1.

Returning to FIG. 1, exposed surfaces of the first plurality ofelectrically conductive members 40, second plurality of electricallyconductive members 42, the first plated through hole 50, and the secondplated through hole 52 are preferably oxidized. The oxidization improvesthe ability of the surfaces of the first plurality of electricallyconductive members 40 and of the second plurality of electricallyconductive members 42 to subsequently bond with the resin 82 of FIG. 3and the resin 92 of FIG. 5, respectively. For example, if the exposedsurfaces include copper, then the oxidation may be accomplished bychloriting; i.e., by applying a solution of sodium hypochloride to saidexposed surfaces. After oxidizing (or chloriting), it is preferred tovacuum bake the multi-layered interconnect structure 18, at atemperature preferably between about 100 EC and about 130 EC for a timeof at least about 60 minutes, to remove moisture from the laminate.

For the preferred dielectric resin, Step 70 further includes (after theaforementioned oxidation): placing the resin coated metal 80 on thesublayer 32 of the first dielectric layer 28 and on the first pluralityof conductive members 40 with the metal foil 83 exposed, and placing theresin coated metal 90 on the sublayer 38 of the second dielectric layer34 and on the second plurality of electrically conductive members 42with the metal foil 93 exposed, as shown in FIG. 6. The electronicconfiguration 8 of FIG. 6 includes the resin coated metal 80 of FIG. 3,the resin coated metal 90 of FIG. 5, and a portion of the multi-layeredinterconnect structure 10 of FIG. 1. Next, the electronic configuration8 of FIG. 6 is pressurized in a range of about 1000 psi to about 2000psi at an elevated temperature between about 180 EC and about 210 EC fora time of at least about 90 minutes. The pressurization and elevatedtemperatures causes the dielectric resins 82 and 92 to flow and becomecured. The pressurization and elevated temperature adhesively laminates:the dielectric resin 82 of the resin coated metal 80 to the sublayer 32of the first dielectric layer 28 and to the first plurality ofelectrically conductive members 40; and the dielectric resin 92 of theresin coated metal 90 to the sublayer 38 of the second dielectric layer34 and to the second plurality of electrically conductive members 42.Additionally, the pressurization and elevated temperature causes thedielectric resin 82 and the dielectric resin 92 to substantially fill(i.e., completely fill aside from air pockets and/or air bubbles) thefirst plated through hole 50 and the second plated through hole 52, asshown in FIG. 7. After the pressurization, the metal foil 83 and themetal foil 93 are removed in a manner known to one of ordinary skill inthe art, such as by etching. FIG. 7 depicts FIG. 6 after the electronicconfiguration 8 has been pressurized, and after the metal foils 83 and93 have been removed. Following the pressurization and removal of themetal foils 83 and 93, the remaining dielectric resin 82 in FIG. 7 isthe third dielectric layer 46 in FIG. 1, and the remaining dielectricresin 92 of FIG. 7 is the fourth dielectric layer 48 in FIG. 1. Thesurface 87 of the dielectric resin 82 is rough, and complementary to therough surface 84 of the metal foil 83 of FIG. 3. The surface 97 of thedielectric resin 92 is rough, and complementary to the rough surface 94of the metal foil 93 of FIG. 3. The roughness of the surface 97 of thedielectric resin 92 facilitates good adhesion of subsequent copperplating on the dielectric resin 92, as discussed infra in conjunctionwith step 72.

Step 72, denoted in FIG. 2 in relation to FIG. 1, includes forming firstpluralities of microvias 55 in the third dielectric layer 46, and secondpluralities of microvias 54 in the fourth dielectric layer 48, by aprocess of removing portions of the third dielectric layer 46 and thefourth dielectric layer 48 to form first and second pluralities ofopenings and exposing at least portions of selected ones of the firstand second pluralities of electrically conductive members 40 and 42,respectively. The openings form internal walls of the consequent firstand second pluralities of microvias 55 and 54, respectively. The firstand second pluralities of microvias 55 and 54 can be formed by a processof mechanical drilling, etching, or preferably laser ablating the thirdand fourth dielectric layers 46 and 48, respectively. If the first andsecond pluralities of microvias 55 and 54 are formed by laser ablation,then the first and second pluralities of microvias microvias 55 and 54are preferably cleaned to remove particulate matter generated by thelaser ablating, employing any hole-cleaning process that is known to oneof ordinary skill in the art, such as by: applying a swelling agent,treating with a potassium permanganate oxidizing material, and using anacid rinse to complete the cleaning.

The internal walls of the first and second pluralities of microvias 55and 54 are then plated with a suitable metal, preferably copper, to formconductive layers on said openings, forming electrically conductiveconnections from the internal walls of the third dielectric layer 46 andfourth dielectric layer 48 to selected ones of the exposed firstpluralities of electrically conductive members 40 and the exposed secondpluralities of electrically conductive members 42, respectively. Theplating of the internal walls may be accomplished by any method known toone of ordinary skill in the art. With copper plating, for example, aseeding material (e.g., tin palladium) may be applied to the surface 97of the dielectric resin 92 to serve as a catalyst for electrolesslyplating a thin layer (e.g., 1 to 3 microns) of copper on the surface 97,followed electroplating a thicker layer (e.g., 1 mil) of copper. Theroughness of the surface 97 of the dielectric resin 92 facilitates goodadhesion the copper plating on the dielectric resin 92. Copper is thenselectively removed, such as by etching, from a portion of the surface97, leaving the remaining copper plating on the internal walls and alsoin the form of any desired copper pads surrounding (and conductivelycoupled to) the copper plating on the internal walls of the first andsecond pluralities of microvias 55 and 54.

A solder paste is then applied to the plated first and secondpluralities of microvias 55 and 54, respectively, the preferred solderpaste being a low melt solder paste such as a eutectic solder paste. Anexample of suitable eutectic solder paste that can be used is Alpha 3060from Alpha Metals (Jersey City, N.J.). The microvias 55, together withthe suitable metal plating on the internal walls of the microvias 55,may be denoted as a plated blind via. Similarly, the microvias 54,together with the suitable metal plating on the internal wall of themicrovias 54, may also be denoted as a plated blind via.

Referring to step 74, the solder paste can then be reflowed to form partof the first and second pluralities of solder connections 47 and 20 onthe first and second pluralities of electrically conductive members 40and 42, respectively.

Next, the semiconductor chip 12 is conductively coupled to the firstplurality of microvias 55 by the plurality of contact members 16 (e.g.,C4 solder balls), and the circuitized substrate 100 is conductivelycoupled to the second plurality of microvias 54 by the second pluralityof solder connections 20 (e.g., BGA solder balls). As stated supra, anyelectronic device (e.g., a semiconductor chip) may be conductivelycoupled to a microvia of the first plurality of microvias 55, and anyelectronic device (e.g., a circuitized substrate) may be coupled to amicrovia of the second plurality of microvias 54. Also as stated supra,one microvia (or plated blind via), in addition to the first pluralityof microvias 55, in the third dielectric material 46 is within the scopeof the present invention, and one microvia (or plated blind via), inaddition to the second plurality of microvias 54, in the fourthdielectric material 48 is within the scope of the present invention.

Referring to FIG. 1, a method of making the electronic package 10comprises the following steps. First a semiconductor chip 12 is providedhaving a first surface which includes a plurality of contact members 16.The plurality of contact members 16 can be pads, columns, or balls(i.e., spheres) of high melt solder. High melt solder is defined as asolder having a melting point above about 230° C. Preferably, theplurality of contact members 16 comprises solder balls. Next, amulti-layered interconnect structure 18, as described above, isprovided. The multi-layered interconnect structure 18 includes a firstplurality of solder connections 47, a first plurality of platedmicrovias 55 including a first layer of reflowed solder paste thereon.The first layer of reflowed solder paste may be formed by applying thefirst solder paste to the plurality of plated microvias 55 followed byreflowing the first solder paste. A second layer of solder paste, havinglow melt solder paste (preferably eutectic solder paste), can be appliedto the plurality of first solder connections 47 and reflowed, and thesemiconductor chip's contact members 16 are each brought in contact withrespective ones of the first plurality of solder connections 47 bypositioning respective ones of the contact members 16 of thesemiconductor chip 12 against respective ones of the first plurality ofsolder connections 47. This is done by positioning and aligning thesemiconductor chip contact members 16 onto the reflowed solder paste.The reflowed solder paste may be shaped or contoured so as toaccommodate the geometrical shape of contact members 16. For example,the reflowed solder paste may be shaped to have a flat top surface so asto accommodate contact members 16 having a spherical shape. The reflowedsolder paste is then reflowed again and molten solder covers the exposedarea of the plurality of microvias 55 and partially wicks up theexternal walls of contact members 16 of the semiconductor chip 12. Uponcooling, the molten solder solidifies and forms an electrical connection47 between the semiconductor chip 12 and the multi-layered interconnectstructure 18. The fact that the semiconductor contact members 16, have ahigher melting point than the solder paste results in a solder standoffas well as an electrical connection between the semiconductor chip 16and the multi-layered interconnect structure 18. This aides in reducinga portion of the strain between the semiconductor chip 12 and themulti-layered interconnect structure 18 during operation of the package.

The electronic package 10 of the present invention can be assembled to acircuitized substrate 100 having a plurality of contact pads 103 on oneof its surfaces 104. As described, these contact pads 103 can becomprised of copper or aluminum or another suitable metal and can becoated with a layer of solder paste (not shown). The second plurality ofsolder connections 20 (e.g., solder balls or solder columns) of themulti-layered interconnect structure 18 are placed in contact with thesolder paste on the contact pads 103 of the circuitized substrate 100.The solder paste and second solder connections 20 are reflowed andcooled forming an electrical connection between the multi-layeredinterconnect structure 18 and the circuitized substrate 100. Thesequence of assembly of the semiconductor chip 12 to the multi-layeredinterconnect structure 18, followed by assembly of the multi-layeredinterconnect structure 18 to the circuitized substrate 100, can easilybe modified. For example, the multi-layered interconnect structure 18can be assembled to the circuitized substrate 100, followed by assemblyof the semiconductor chip 12 to the multi-layered interconnect structure18.

The electronic package 10 described herein provides signal and powerdistribution characteristics which complement high performanceelectrical demands of future semiconductor chips and is particularlysuited for interconnecting high I/O (greater than 400 I/O)semiconductors. A low impedance power distribution is achieved using thesolid copper power planes and high density plated through holes underthe semiconductor chip, which allow multiple vertical power feeds to thesemiconductor chip. Further electrical performance benefits andpreservation of signal integrity (fast signal propagation, low signalcapacitance and coupled noise, and matched characteristic impedance) areachieved in the electronic package by use of low dielectric constantPTFE material (Er <3), the signal carrying conductors being arrangedinternally in a shielded arrangement, and a direct short path length forthe semiconductor chip contact members to the signal carryingconductors.

The scope of the present invention includes the electronic package 10 ofFIG. 1 with removal of: the first dielectric layer 28, the seconddielectric layer 34, and the thermally conductive layer 22.

While the electronic package 10 described herein includes a firstplurality of electrically conductive members 40, it is within the scopeof the present invention for the electronic package 10 to additionallyinclude at least one first electrically conductive member 40.

While the electronic package 10 described herein includes a secondplurality of electrically conductive members 42, it is within the scopeof the present invention for the electronic package 10 to additionallyinclude at least one second electrically conductive member 42.

While the electronic package 10 described herein includes a firstplurality of microvias 55, it is within the scope of the presentinvention for the electronic package 10 to additionally include at leastone first microvia 55.

While the electronic package 10 described herein includes a secondplurality of microvias 54, it is within the scope of the presentinvention for the electronic package 10 to additionally include at leastone second microvia 54.

While the electronic package 10 described herein includes a firstplurality of solder connections 47, it is within the scope of thepresent invention for the electronic package 10 to additionally includeat least one first solder connection 47.

While the electronic package 10 described herein includes a secondplurality of solder connections 20, it is within the scope of thepresent invention for the electronic package 10 to additionally includeat least one second solder connection 20.

While the electronic package 10 described herein includes a plurality ofcontact members 16, it is within the scope of the present invention forthe electronic package 10 to additionally include at least one contactmember 16.

While the electronic package 10 described herein includes a plurality ofcontact pads 103, it is within the scope of the present invention forthe electronic package 10 to additionally include at least one contactpad 103.

While the electronic package 10 described herein includes a plurality ofconductive bonding pads 56, it is within the scope of the presentinvention for the electronic package 10 to additionally include at leastone conductive bonding pad 56.

While the electronic package 10 described herein includes a plurality ofthrough holes 50 and 52, it is within the scope of the present inventionfor the electronic package 10 to additionally include at least onethrough hole 50 or 52.

Second Dielectric Material Embodiment

As a second dielectric material embodiment of the present invention,layers 29, 30 and 32 of first dielectric layer 28, and layers 35, 36 and38 of second dielectric layer 34 alternatively comprise a liquid crystalpolymer (LCP) dielectric. All aspects of the first dielectric materialembodiment of the present invention, described supra, also apply to thesecond dielectric material embodiment except for those aspects whichspecifically relate to the use of LCP dielectric material as describedinfra in this subsection.

LCP dielectric materials have many positive attributes for formingdielectric layers, including good dielectric properties, low cost, andgood mechanical properties. LCP dielectric materials have somecharacteristics similar to those of polyimides, such as good tearresistance and good stretching resistance, which make LCP dielectricmaterials suitable for processing (e.g., circuitizing, plating, etc.) invery thin layers. LCP films may offer advantages over polyimide filmssuch as better electrical properties, better moisture resistance, betterdimensional stability, and lower cost. However, to form multilayerstructures with either LCP or polyimide films generally requires the useof adhesive dielectric films. The present invention discloses how tocause LCP dielectric material to adhere to a layer of material (e.g., ametal layer or a dielectric layer) without need for an extrinsicintervening adhesive layer, which reduces layer thickness, processingcosts, and material costs. In addition, LCP dielectric films of thistype are flame retardant without the use of halogen based additives.Multilayer composites made with these dielectrics may also be flameretardant without the use of halogens.

A commercially available LCP dielectric material that may be used inconjunction with the present invention is the BIAC thermotropic liquidcrystal polymers which exhibit thermoplastic behavior and aremanufactured in sheet or roll form by W.L. Gore & Associates, Inc.Information on the BIAC liquid crystal polymers may be obtained at theweb site: http//www.gore.com/electronics. Another commercially availableLCP dielectric material that may be used in conjunction with the presentinvention is the ZYVEX LCP thermotropic liquid crystal polymers whichexhibit thermoplastic behavior and are manufactured in roll form by theRogers Corporation. Generally, any LCP dielectric material ispotentially usable with the present invention, depending on the materialproperties desired in a given application.

U.S. Pat. No. 6,274,242 (Onodera et al. 2001) (“Onodera '242”), herebyincorporated by reference in its entirety, discloses a method of makingLCP films which include well known thermotropic liquid crystal polyesterand thermotropic liquid crystal polyester amide. Said LCP films areprepared from four classes of compounds identified in Tables 1-4 ofOnodera '242. Examples of resultant LCP structural units derived fromthe four classes of compounds are illustrated in Table 5 of Onodera'242. The LCP dielectrics disclosed in Onodera '242 are merelyexemplary, and many other LCP dielectrics are within the scope of thepresent invention. Generally, any method known to one of ordinary skillin the art may be used to make the LCP dielectric material.

A LCP dielectric may exist in one of three phases: a liquid crystalphase (e.g., nematic, smectic, cholesteric), an isotropic phase, and achemically unstable phase, which respectively correspond to threetemperature domains, namely a liquid crystal temperature domain, anisotropic temperature domain, and a chemically unstable temperaturedomain.

In the liquid crystal phase or liquid crystal temperature domain,localized molecular regions or domains of the LCP dielectric comprisepolymer chains, which are directionally ordered (i.e., anisotropicallydistributed) such as by processing. In the liquid crystal phase,different localized molecular domains may have different directionalordering, and many localized molecular domains may have little or nodirectional ordering. These polymer chains are typically less than fullyrigid. Such a localized molecular domain having directional ordering mayinclude domains of molecules and/or groups of adjacent molecules, suchthat the spatial extent of the localized molecular domain is of theorder of a thousand or hundreds of angstroms or less. Macroscopicmaterial properties of the LCP dielectric (e.g., coefficient of thermalexpansion (CTE), dielectric constant, thermal conductivity, etc.) aresensitive to the directional order in the localized molecular regions,and material properties of LCP dielectric materials are anisotropic inaccordance with the directional ordering. The macroscopic materialproperties of the LCP dielectric are also dependent on the shape, size,shape distribution, and size distribution of the localized molecularregions.

The LCP dielectric material is manufactured by techniques known to oneof ordinary skill in the art to produce a directional ordering thatprovides the desired material properties in the liquid crystal phase.Such techniques may include, inter alia, two-dimensional shear impartedto the LCP dielectric material through film extrusion or throughstretching in the roll direction and stretching in the direction normalto the roll direction, as the LCP dielectric material is being unrolledat a prescribed temperature and velocity. The shear may alternatively beimparted by strong polarizing electric fields.

The LCP dielectric material remains in the liquid crystal phase if itstemperature is in the liquid crystal temperature range; i.e., below atemperature called the nematic-to-isotropic transition temperature(T_(NI)). Thus, T_(NI) represents the transition from the liquid crystalphase to the isotropic phase of a LCP dielectric material. The numericalvalue of T_(NI) depends of the specific LCP dielectric material beingutilized. Additionally, the directional ordering and consequentmacroscopic material properties of the LCP dielectric material areessentially invariant to changes in temperature provided that thetemperature remains within the liquid crystal temperature range and doesnot depart from the liquid crystal temperature range. Macroscopicmaterial properties are preserved as temperature is varied within theliquid crystal temperature domain, because there is insufficient thermalenergy in the liquid crystal phase to reorient the directionality ofpolymer chains of the LCP dielectric material (i.e., to overcome theinter-molecular attractive forces).

The LCP dielectric material plastically deforms when subject to highpressure in the liquid crystal phase. For example, in the manufacturingof chip carriers, the high pressure may result from a combination ofapplied normal pressure and local geometrical irregularities such asstress concentrations resulting from surface roughness, signal lines,vias, etc. Thus if the LCP dielectric material is laminated to a layerof material (comprising dielectric, metal, etc.) at high pressure and atelevated temperature within the liquid crystal phase, then the LCPdielectric material will plastically deform and conform to themacroscopic geometry of the surface and surface features (e.g., vias) ofthe layer of material. This capability of the LCP dielectric material toplastically conform, under sufficient pressurization while in the liquidcrystal phase during the dwell time, to the surface and surface featuresof an adjacent layer is an unexpected result determined throughexperimentation by the inventors of the present invention, and serves asa foundational basis for the present invention. With the presentinvention, LCP dielectric material may be laminated to an adjacentsurface of a layer of material through elevation of temperature withinthe liquid crystal temperature domain, and under sufficientpressurization to induce plastic deformation and consequent adhesion tothe adjacent surface, while preserving its macroscopic materialproperties. This process of plastic adhesion does not require thepresence of an extrinsic adhesive layer to bond the LCP dielectricmaterial to the adjacent layer.

FIG. 8 depicts a localized molecular domain 200 in the nematic typeliquid crystal phase with directional ordering of polymer chains, inaccordance with embodiments of the present invention. The domain 200includes polymer chains 201-208 ordered directionally such that theaverage directional orientation, angularly integrated over thedirectional orientations of the polymer chains 201-208, is approximatelyin the direction 210. Such angular integration may be performed invarious ways as is known to one of ordinary skill in the art (e.g.,different components of a given polymer chain may be weighteddifferently in the angular integration). Regardless of this specificdefinition used to define the angular average, however, the angulardistribution of the directional orientations is clearly anisotropic suchthat there is a preferred direction at or near the direction 210.

In this illustration, each of polymer chains 201-208 is shown as alinear chain of alternating rigid and semi-flexible components. Forexample, polymer chain 205 comprises the sequence of polymer components221-226, wherein components 221, 223, and 225 are rigid components, andwherein components 222, 224, and 226 are semi-flexible components. Anexample of a rigid component is a polymer having a polymer backbone thatincludes repeating units of substituted aromatic rings (e.g., benzene,biphenyl, naphthalene, etc.) such as disclosed in U.S. Pat. No.6,274,242 (Onodera et al, see Tables 1, 2, 3, 4, and 5) and U.S. Pat.No. 5,900,292 (Moriya, see formulae 1, 2, 3, and 4). The rigid componentmay have reactive functional groups (e.g., hydroxy, amine, cyanate,carboxylic acid, and combinations thereof, etc.). An example of asemi-flexible component is a polymer having a polymer backbone thatincludes repeating units such as aliphatic segments (e.g., oxymethyleneunits, oxyethylene units, vinyl ether units, siloxanes units, etc.). Thesemi-flexible component may have chemically functional groups (e.g.,hydroxy, amine, cyanate, carboxylic acid, and combinations thereof,etc.). Such a polymer may be prepared in two ways. First, the ends ofadjacent rigid and semi-flexible components may be chemically coupled toeach other to form esters, ethers, amides, etc. links in the polymerchain. Second, the ends of adjacent rigid components may be chemicallycoupled to each other to form ester, ether, amides (etc.) links in thepolymer chain. In this second case, the links or connecting segments(esters, ethers, amides, etc.) would be the only semi-flexiblecomponent.

While FIG. 8 shows polymer chains 201-208 as each being a linear chainof alternating rigid and semi-flexible components, any linear chain ofrigid and semi-flexible components (e.g., a non-alternating sequence ofrigid and semi-flexible components) is within the scope of a localizedmolecular domain. While FIG. 8 shows polymer chains 201-208 as eachbeing a linear chain of components, any polymer chain topography iswithin the scope of a localized molecular domain. For example, alocalized molecular domain may also or alternatively include a chainstructure that comprises one or more side chains linked to a linearchain. While FIG. 8, shows a two-dimensional representation of linearchains, the localized molecular domain generally has chain structures,which are oriented in three-dimensional space. For example, portions ofany of the polymer chains 201-208 may extend above or below the depictedplane shown in FIG. 8. Accordingly, FIG. 8 may be viewed as a projectionof a three-dimensional localized molecular domain onto a two-dimensionalsurface and the chains pictured may continue above and below thedepicted plane.

In the isotropic phase or isotropic temperature domain, which exists attemperatures at or above the nematic-to-isotropic transition temperature(T_(NI)), there is sufficient available thermal energy to permitmolecular diffusion and motion to change the directional ordering withinthe LCP dielectric. Thus as temperature changes from below T_(NI) toabove T_(NI), there is a loss of directional order and the directionalorientations become more random. As a consequence, macroscopic materialproperties will generally change in the temperature transition frombelow T_(NI) to above T_(NI), since the macroscopic material propertiesare sensitive to direction orientations of polymer chains in the LCPdielectric material, as described supra. When lamination of LCPdielectric material to a layer of material is performed at a temperaturein the isotropic temperature range, the LCP dielectric material softensand liquifies and thus flows into the macroscopic geometry of thesurface and surface features of the layer of material. Upon subsequentcooling its thermal history and processed-in directional order ischanged. In contrast, when lamination of LCP dielectric material to alayer of material is performed at a temperature in the liquid crystaltemperature range with sufficient pressurization, the LCP dielectricmaterial does not flow but rather plastically deforms into themacroscopic geometry of the surface and surface features of the layer ofmaterial, as explained supra. The present invention teaches laminationof LCP dielectric material to a layer of material only at a temperaturein the liquid crystal temperature range and thus teaches an inventionthat preserves macroscopic material properties during the laminatingprocess. The lower temperature in the liquid crystal temperature rangeprevents any risk of the material melting or of domain re-orientation oflarge regions. An additional advantage is that no extrinsic adhesivelayer is needed to bond the LCP dielectric material to the layer ofmaterial.

FIG. 9 depicts a localized molecular domain 250 in the isotropic phasein which there is little or no directional ordering of polymer chains,in accordance with embodiments of the present invention. The domain 250includes polymer chains 251-261 ordered directionally such that theaverage directional orientation, angularly integrated over thedirectional orientations of the polymer chains 201-208, is approximately“zero”; i.e., there is essentially no preferred angular orientation ordirection associated with the domain 250.

Each of polymer chains 251-261 is shown as a linear chain of alternatingrigid and semi-flexible components. For example polymer chain 259comprises the sequence of polymer components 271-277, wherein components271, 273, 275, and 277 are semi-flexible components, and whereincomponents 272, 274, and 276 are rigid components. The rigid andsemi-flexible components in the polymer chains of FIG. 9 arerespectively analogous to the rigid and semi-flexible components in thepolymer chains of FIG. 8, and the examples of rigid and semi-flexiblepolymer components discussed supra in conjunction with FIG. 8 likewiseapply to the rigid and semi-flexible components of FIG. 9.

While FIG. 9 shows polymer chains 251-261 as each being a linear chainof alternating rigid and semi-flexible components, any linear chain ofrigid and semi-flexible components (e.g., a non-alternating sequence ofrigid and semi-flexible components) is within the scope of a localizedmolecular domain. While FIG. 9, shows polymer chains 251-261 as eachbeing a linear chain of components, any polymer chain topography iswithin the scope of a localized molecular domain. For example, alocalized molecular domain may also or alternatively include a chainstructure that comprises one or more side chains linked to a linearchain. While FIG. 9 shows a two-dimensional representation of linearchains, the localized molecular domain generally has chain structureswhich are oriented in three-dimensional space. For example, portions ofany of the polymer chains 251-261 may extend above or below the depictedplane shown in FIG. 9. Accordingly, FIG. 9 may be viewed as a projectionof a three-dimensional localized molecular domain onto a two-dimensionalsurface and the chains pictured may continue above and below thedepicted.

In the chemically unstable phase or chemically unstable temperaturedomain, which occurs at significantly higher temperatures than thenematic-to-isotropic transition temperature (T_(NI)), there issufficient available thermal energy to cause chemical decompositionwithin the LCP dielectric. The chemically unstable phase is not relevantto the present invention.

The present invention discloses a method for bonding LCP dielectricmaterial to a layer of material (e.g., a dielectric layer or a metallayer or a combination thereof). As background for the presentinvention, the following discussion describes tests performed by theinventors of the present invention. In tests dating to 1994, the presentinventors have attempted melt processing of LCPs, as known and taught inthe art, to build multi-layer structures, with the approach of usingprecise temperature control to laminate the materials at temperaturesjust above or just below the “melting” temperature (i.e., T_(NI)) asdetermined by differential scanning calorimetry and by parallel platerheometry. These experiments are characterized by inconsistent resultsin adhesion, laminate thickness, edge squeeze out, and importantly thephysical properties of resulting laminate. Of particular note are theinconsistent changes that occurred in the coefficient of thermalexpansion. This is a clear indication that the properties of the baselaminate have been changed, essentially destroying their utility for theuse intended, and therefore requiring the use of adhesive layers to formmulti-layer circuits.

In contrast, experiments performed during June through September of 2002have shown that by lowering the temperature to below T_(NI), consistentadhesion is achieved without altering the properties of the baselaminate. For example, Gore BIAC material, having a 2 mil thickness with15 um of copper cladding on each side, was utilized. Etching away thecopper, the inventors determined that the coefficient of thermalexpansion (CTE) was approximately 20 to 25 ppm/EC as received from thevendor. A thermal mechanical analyser was used to determine the CTE invarious locations on a panel that measured approximately 13×18 inches.The CTE was measured in both x-coordinate and y-coordinate directions(i.e., in the two directions that are perpendicular to the thicknessdirection of the BIAC layer and also perpendicular to each other). Botha film-fiber configuration and a more conventional contacting probe wereused to make these measurements.

After characterizing the properties of individual plies of the LCP,multi-ply laminates were prepared. The laminates comprised 4 ply and 6ply thick composites formed using the Gore BIAC material, from which thecopper cladding had been etched away. The parts were subjected to alamination process that involved heating to 560 EF at a heatup rate of15 EF per minute, next followed by a dwell time of approximately 20 to30 minutes, and then followed by cooling at approximately 20 EF perminute to room temperature. Dwell time is defined herein, including inthe claims, as a time interval during which the part being laminated issubjected to the highest temperature (within a reasonable temperaturetolerance of said highest temperature due to statistical scatter andother minor variations) that the part experiences during the entirelamination process, said entire lamination process including allprocessing steps. Note that the maximum temperature of 560 EF is lessthat the liquid crystal transition temperature (assumed herein to beessentially the same as T_(NI)) of 635 EF of the Gore BIAC material. Thelamination was accomplished using a flat bed press with electricallyheated steel platens. The pressure was maintained at 2500 psi throughoutthe processing. Stainless steel planishing plates and copper releasesheets were employed, as well as interleaving layers ofpolytetrafluoroethylene (PTFE) and copper to make a press pad above andbelow the tooling. Upon removal from the press, the inventors found noevidence of dielectric squeeze out at the edges of the laminate.

The thermal mechanical analysis was repeated and determined that thex-coordinate and y-coordinate (in-plane) CTE were unaltered by thelamination process. Adhesion tests were performed, using a 180 degreepull at 1 inch per minute, and an inner layer adhesion strength inexcess of 6 lbf/inch was determined.

The same lamination process was repeated to evaluate the extent to whichtopography associated with realistic circuit features could beaccommodated. A layer of Roger 2800 dielectric (PTFE/SiO2 filler) wasused, and the layer of Roger 2800 dielectric had surface featuresincluding 12 um thick Cu formed into the circuit line of 30 to 50 um inwidth. The layer of the Gore BIAC LCP (50 um thick) was positioned abovethe Roger 2800 dielectric surface and the lamination was performed atthe previously described conditions. Upon removal and subsequent crosssectioning, it was found that the circuit features were completelyencapsulated. As before, there was no edge squeeze out. Adhesion testingshowed an inner layer adhesion strength in excess of 4 lbf/inch betweenthe LCP and Roger 2800 dielectric.

In another experiment, standard photolithography techniques were appliedto copper clad LCP (i.e., 15 um copper cladded to Gore BIAC LCP) to forma pattern of clearance holes ranging from 50 to 500 um diameter on oneof the copper surfaces. A second sheet of Gore BIAC LCP (with copperremoved) was placed against the side of the first sheet that had theclearance holes. After repeating the lamination process as describedsupra, the part was cross-sectioned and it was determined that the holeswere completely filled with BIAC LCP dielectric material. Again therewas no evidence of edge squeeze out, and the adhesion was consistentacross the panel.

The lamination experiments were first performed in panel sizes as smallas 4″×4″ in an electrically heated 75 ton laboratory press with novacuum enclosure, manufactured by PHI Corporation. The results wereduplicated in an electrically heated 125 ton Wabash press with a vacuumenclosure, and finally in a 600 ton electrically heated TMP press in13″×18″ format. These larger samples were used to establish theuniformity of adhesion, hole fill, and physical properties over a panelsize that would be practical in manufacturing.

Based on the preceding experiments and supplementary analysis, which areconsistent with the model (described supra) of directional orderingcharacteristics of LCP dielectric materials as being differentiated inthe liquid crystal and isotropic phases, the basic technique of thepresent invention for laminating a LCP dielectric material to a layer ofmaterial (e.g., a dielectric layer or a metal layer or a combinationthereof) is to perform the lamination at a temperature T wholly in theliquid crystal temperature range (i.e., T<T_(NI)) with no excursion intothe isotropic temperature range, under sufficient pressurization and fora sufficient time to cause the LCP dielectric material to be effectivelylaminated to the layer of material,

For the Gore BIAC LCP material, T_(NI) is about 635 EF. For the Gore BIALCP material, the maximum lamination temperature should be less than 635EF; however, due to temperature uncertainties and spatial variation, amaximum processing temperature for lamination may be about 620 EF, andrepresentative lamination temperature ranges include, inter alia, 540 EFto 620 EF and 545 EF to 580 EF. For the Rogers ZYVEC LCP material,T_(NI) is about 536 EF. For the Rogers ZYVEC LCP material, the maximumlamination temperature should be less than 536 EF; however, due totemperature uncertainties and spatial variation, a maximum processingtemperature for lamination may be about 520 EF, and representativelamination temperature ranges include, inter alia, 440 EF to 520 EF and465 EF to 590 EF.

Although the preceding experiments were performed at a pressure of 2500psi, the present inventors have used pressure in the range of 1000 to3000 psi and achieved good adhesion. It was found that an improvement inuniformity correlated with increasing pressure. The effectiveness of thepressure depends on the aspect ratio of the features that must be filledduring the lamination. The testing performed by the inventors thus farindicate that a range in pressure of 2000 to 2500 psi is particularlyeffective, as well as practical and economical for use in a conventionalmanufacturing environment. Extreme pressures can have the drawback ofshortened life for the tooling and platens, and also require increasedcapacity for the press itself.

The dwell times used by the present inventors include keeping thematerial LCP dielectric pressurized at maximum temperature for durationsas short as 2 to 5 minutes to durations as long as 60 minutes. It wasfound that no undesirable “edge squeeze out” or other evidence of excessflow occurs with the longer times, although some improvement in adhesionuniformity may result. Thus the maximum dwell time for temperature andpressure should generally be at least 2 minutes, and applicable rangesof dwell times include, inter alia, 2 to 60 minutes and 15 to 30minutes. A minimum dwell is required to ensure temperature uniformity.However, the quality of the filling of features should improve withincreasing dwell time. On the other hand, shorter times are favorablefor economy of manufacturing, and the shorter dwell times reflect thisgoal of economy. Nonetheless, no upper limit of dwell time has beenobserved by virtue of the resulting properties of the laminates.

Repeating the lamination cycle twice may improve the uniformity ofadhesion, and by repositioning the product in the lamination press(perhaps turning it 180 degrees), the low spots become high spots,resulting in more uniform adhesion, especially along the edges.

In accordance with the discussion of LCP dielectric materials and thetesting relating to lamination of LCP dielectric materials to a layer ofmaterial, the LCP material used in the present invention may be apartially ordered liquid crystal polymer resulting from variousprocessing steps which partially orient the microscopic liquid crystaldomains directionally during the manufacturing of the LCP dielectric.Higher order smectic (i.e., orientational and positional order) phasesmay also be present. Although the preceding discussion focused onhomogenous LCP dielectrics, the adhesiveless lamination process of thepresent invention is also applicable to LCP materials that containfillers, such as ceramic or organic, particulate or fiber-like, or evenmetallic particles. Further, expanded PTFE as a reinforcement in LCPmaterials in within the scope of the present invention.

The desired material properties for the LCP dielectric material, in thecontext of the present invention, are application dependent. For themulti-layered interconnect structure described supra in conjunction withFIGS. 1-7, as well as for other applications, material properties maycomprise: in-plane CTE (i.e., CTE in direction perpendicular to thethickness direction of a LCP dielectric layer) of about 10 to 25 ppm/°C.; dielectric constant of about 2.5 to 3.0; Young's modulus of about 3to 6 GPa; dissipation factor of less than about 0.003; and moistureabsorption of less than about 0.2% for 96 hours at 121° C. and 2 atm.The thickness of the LCP dielectric layers can vary according to thedesired design performance characteristics of the multi-layeredinterconnect structure (e.g., the multi-layered interconnect structure18 of FIG. 1), and said thicknesses may be about equal if so dictated bydesign performance requirements. For manufacturing efficiency,lamination is typically performed with a “book” that includes multiplepages.

The following discussion discloses two practical methods of performinglamination of a multi-layered interconnect structure (called a “page”),namely flat-bed press lamination (see FIGS. 10-11) and autoclavelamination (see FIG. 12).

FIGS. 10 and 11 illustrate flat-bed press lamination for lamination ofstacked layers that include LCP dielectric material, in accordance withembodiments of the present invention. In FIG. 10, a flat-bed laminationpress 300 is enclosed and structurally supported by a frame 302. FIG. 10depicts a three-opening flat-bed lamination press 300 that has an upperbolster 304, a middle bolster 308, a lower bolster 306, a top platen322, mid-platens 324 and 326, a bottom platen 328, books 311-313, guiderods 320, a hydraulic system 329, a vacuum pump 340, and a vacuumfeedthru 342. The platens 322, 324, 326, and 328 and books 311-313 maybe supported from below by the middle bolster 308 and are constrainedfrom above by the upper bolster 304. The platens 322, 324, 326, and 328are supported laterally and guided vertically by the guide rods 320. Thehydraulic system 329 comprises a hydraulic cylinder 322, hydraulic fluid334, a piston 330, and a pump (not shown) that circulates the hydraulicfluid 334 by use of a supply line (not shown) that is coupled to thepump. The hydraulic cylinder 334 is used to apply pressure to theplatens. Typical operating pressures for the hydraulic fluid 334 are ina range of up to 5000 psi. The pressure applied to the books depends onthe relative size of the book versus the diameter of the hydraulicpiston 330. With the present invention, pressures in a range of, interalia, about 1000 to about 3000 psi may be applied to the product layerswithin the books. The chamber of the press may be subject to a vacuumgenerated by the vacuum pump 340 with the vacuum feedthru 342, so as tominimize oxidation and entrapment of voids during lamination processing.Alternatively, the vacuum pump 340 may be omitted, or turned off and notused during lamination press operation. Not shown are the feedthroughsand supply lines for the platen heating and cooling systems, which couldbe electrically or fluid heated, and fluid cooled.

Book 311 is disposed between top platen 322 and mid-platen 324. Book 312is disposed between mid-platen 324 and mid-platen 326. Book 313 isdisposed between mid-platen 326 and bottom platen 328. While FIG. 10shows three books 311-313, the flat-bed lamination press 300 may processat least one of such books and as many books as can fit geometricallybetween the upper bolster 304 and the middle bolster 308, inconsideration of the thickness in the direction 310 of the platens andthe books. Each of books 311-313 comprises one or more pages, and eachpage comprises multiple layers and/or multilayered structures to belaminated together by pressurization through movement of the piston 330in the direction 310 such that each book is compressed between theplatens that contact the book on each side of the book (e.g., the book312 is compressed between the platens 324 and 326). The multiple layersand/or multilayered structures of each page comprise one or more LCPdielectric layers. Upon actuation of the press, the piston 330 moves upin the direction 310 and platens 322, 324, 326, 328 and come intocontact with books 311-313. The platens that contact the books duringthe lamination process not only provide surfaces for compressing thebooks during lamination, but also provide a heat source for elevatingthe temperature of the LCP dielectric layers in each page of each bookas will be explained infra. An example of a multilayered laminate thatresults from use of the flat-bed lamination press 300 is themulti-layered interconnect structure 18 of FIG. 1 such that each ofdielectric layers 29, 30, 32, 35, 36 and 38 comprise LCP dielectricmaterial.

FIG. 11 shows the detailed structure of book 312 and platens 324 and 326of FIG. 10, in accordance with embodiments of the present invention. Thebook 312 comprises an alternating sequence of plate layers and pagesbetween press pads 362 and 364. In particular, the book 312, comprisesthe alternating sequence of: plate layer 370, page 357, plate layer 380,page 358, and plate layer 390. The plate layer 370 comprises aplanishing plate 372 sandwiched between release sheets 371 and 373. Theplanishing plate 372 assists in planarizing the page 357. Variousconsiderations are made in selecting the material of the planishingplate 372, including its thickness, size, and thermal expansioncharacteristics. In many applications, the planishing plate 372 maycomprise stainless steel. The release sheets 371 and 373 should comprisea material (e.g, copper) that enables the plate layer to be easilydetached from the page 357 after completion of the laminationprocessing. The plate layer 380 comprises a planishing plate 382sandwiched between release sheets 381 and 383, and the planishing plate382 and release sheets 381 and 383 are respectively analogous to theplanishing plate 372 and release sheets 371 and 373. The plate layer 390comprises a planishing plate 392 sandwiched between release sheets 391and 393, and the planishing plate 392 and release sheets 391 and 393 arerespectively analogous to the planishing plate 372 and release sheets371 and 373. The press pads 362 and 364 may include a compliant materialto give more uniform lamination by compensating for spatial thicknessnon-uniformities in the pages and release sheets.

Platens 324 and 326 are similarly constructed. In platen 324, heatingelements 354 may generate heat in any form that is known to one ofordinary skill in the art such as generation of heat by electricalresistance heaters or by a heated circulating fluid (e.g., oil). Inlettube 351 and outlet tube 352 are use to circulate fluid (e.g., air,water, etc.) through the platen 324 for cooling purposes. Platen 324also includes thermocouple ports 353 for using thermocouples to measureplaten 324 temperatures. Platen 324 is bounded by wear plates 355 forplanarizing the book 312 as the book 312 is pressurized. The wear plates355 are thermally conductive and transmit heat generated by the heatingelements 354 to the book 312. The wear plates 355 should have goodthermal conductivity and may comprise hardened steel in someapplications.

FIG. 12 illustrates an autoclave lamination press for lamination ofstacked layers that include LCP dielectric material, in accordance withembodiments of the present invention. In FIG. 12, an autoclave 400comprises a chamber 404 surrounded by an enclosure 402. The chamber 404comprises a vacuum bag 419 enclosed by flexible membrane 418. A book 410is placed within the vacuum bag 419. The vacuum bag 419 can have variousconfigurations, but it must completely envelope the book 410, andprovide some flexibility so that the vacuum bag 419 will conform to thebook 410 upon evacuation (described infra). The vacuum bag 419 and thebook 410 therewithin are placed in the chamber 404 which is then sealed.The vacuum bag 419 may also include a breather ply 409 for the purposeof facilitating complete evacuation of the vacuum bag 419. The vacuumbag 419 with the included book 410 is mechanically supported by acarrier tray 412. The flexible membrane 418 provides a pressure boundarythat interfaces with a pressurized, heated gas 420 (e.g., nitrogen)within the portion of the chamber 404 that is exterior to the flexiblemembrane 418. The pressure differential between the space exterior tothe flexible membrane 418 and the space within the vacuum bag 419 may befurther controlled by evacuating the air from within the vacuum bag 419by a vacuum pump 406 via a vacuum supply line 408. The pressurized,heated gas 420 is supplied to the chamber 404 by a source 414 throughgas inlet tubing 416. Thus the gas 420 is a medium through whichelevated temperature and pressure are applied to book 410 so as tolaminate the pages contained within the book 410. The resultinglaminations are similar to that achieved in a flat bed lamination press,in that compressive stresses normal to the book 410 are achieved.However, the pressure uniformity is generally improved by the use of theautoclave 400, since there is an absence of shear tractions on the outersurface of the book 410. Although FIG. 12 shows one vacuum bag 419, thescope of the present invention also includes a plurality of such vacuumbags within the chamber 404.

For both the flat bed lamination press and the autoclave laminationpress, the temperatures, pressures, and dwell times are in accordancewith the need to laminate one or more layers of LCP dielectric materialto other layers of material, as discussed infra. Thus during thelamination process, the LCP dielectric material should be laminated at atemperature T wholly in the liquid crystal temperature range (i.e.,T<T_(NI)) with no excursion into the isotropic temperature range, undersufficient pressurization and for a sufficient dwell time to cause theLCP dielectric material to be effectively laminated to the layer ofmaterial. For many applications, pressure in the range of 1000 to 3000psi will effectuate good adhesion. The dwell time for maximumtemperature and pressure should generally be at least 2 minutes, andapplicable ranges of dwell times include, inter alia, 2 to 60 minutesand 15 to 30 minutes.

It is known in the art that for lamination of conventional thermosetdielectric layers (e.g. epoxy/glass pre-preg), comparable results (e.g.,with respect to adhesion and flow) can be obtained at reduced pressurein an autoclave versus a flat bed press. This suggests that in the caseof LCP lamination, reduced pressures (perhaps by as much as a factor oftwo) may be effective, and thus desirable for reducing costs associatedwith autoclave lamination.

In addition to use of the flat bed lamination press and the autoclavelamination press for laminating stacked LCP dielectric layers to otherlayers, other lamination press hardware known to one of ordinary skillin the art may be used for accomplishing such laminations in accordancewith the aforementioned conditions on temperature, pressure, and dwelltime.

The lamination process can be used to stack layers of LCP dielectricmaterial with layers of dielectric material (i.e., either LCP dielectricor non-LCP dielectric) or metallic layers, (e.g., signal planes, powerplanes, ground planes, etc), and signals thereof. With such stacking,attention should be given to achieving correct layer to layer alignment.Each copper clad dielectric core can have reference (fiducial) holesthat are used for mechanical pins to provide layer to layer alignment.Both the photolithography steps to form circuit features and thelamination process can utilize these reference holes. Special toolingthat includes plates with corresponding holes that accommodate the pinsare used. The reference holes in the dielectric cores can be formedprior to and used as a reference for the photolithography steps, oralternately, they can be formed after the photolithography steps andthen drilled in reference to the circuit features. This technique allowsfor calculation of the optimal location for the pin holes, given thatsome distortion or size change of the core may have occurred during thephotolithography (especially for thin layers). A further alternative isto use a means of optical alignment, where the circuit features on thecores are detected, and then the layers are positioned and held in placefor the lamination process, without using any pins.

The method described supra in conjunction with FIG. 2 for forming themulti-layered interconnect structure 18 of FIG. 1 in accordance with thefirst dielectric material embodiment is modified as follows forimplementing the second dielectric material embodiment in which layers29, 30 and 32 of first dielectric layer 28, and layers 35, 36 and 38 ofsecond dielectric layer 34, comprise a LCP dielectric. Note that thefirst dielectric layer 28 may comprise a first LCP dielectric material,and the second dielectric layer 34 comprise a second LCP dielectricmaterial. The first LCP dielectric material and the second LCPdielectric material may be a same LCP dielectric material.Alternatively, the first LCP dielectric material and the second LCPdielectric material may be a different LCP dielectric material.

Step 62 of FIG. 2 is to be performed as described supra in conjunctionwith the first dielectric material embodiment.

Step 64 of FIG. 2 is to be modified such that the pressurization andtemperature elevation described supra in conjunction with the firstdielectric material embodiment is to be replaced by the pressurizationand temperature elevation described supra in conjunction with the seconddielectric material embodiment for laminating LCP dielectric material toother layers of material. In particular, the lamination temperature T isto be wholly in the liquid crystal temperature range (i.e., T<T_(NI))with no excursion into the isotropic temperature range, under sufficientpressurization (e.g., 1000 to 3000 psi) and for a sufficient dwell timeto cause the LCP dielectric material to be effectively laminated to thelayer of material. The dwell time for maximum temperature and pressureshould generally be at least 2 minutes, and applicable ranges of dwelltimes include, inter alia, 2 to 60 minutes and 15 to 30 minutes.

Steps 66 and 68 of FIG. 2 are to be performed as described supra inconjunction with the first dielectric material embodiment.

Performance of step 70 of FIG. 2 depends on the choice of material forthe third dielectric layer 46 and the fourth dielectric layer 48. If thedielectric layers 46 and 48 include a high density interconnect layersuch as a resin comprising a modified polyphenylene ether, then step 70of FIG. 2 is to be performed as described supra in conjunction with thefirst dielectric material embodiment. However, the dielectric layers 46and 48 may alternatively include LCP dielectric material. Thus, if oneor both of the dielectric layers 46 and 48 include LCP dielectricmaterial, then step 70 of FIG. 2 is to be modified (for whichever orboth of dielectric layers 46 and 48 include LCP dielectric material)such that the pressurization and temperature elevation described suprain conjunction with the first dielectric material embodiment is to bereplaced by the pressurization and temperature elevation described suprain conjunction with the second dielectric material embodiment forlaminating LCP dielectric material to other layers of material. Inparticular, the lamination temperature T is to be wholly in the liquidcrystal temperature range (i.e., T<T_(NI)) with no excursion into theisotropic temperature range, under sufficient pressurization (e.g., 1000to 3000 psi) and for a sufficient dwell time to cause the LCP dielectricmaterial to be effectively laminated to the layer of material. The dwelltime for maximum temperature and pressure should generally be at least 2minutes, and applicable ranges of dwell times include, inter alia, 2 to60 minutes and 15 to 30 minutes.

Steps 72 and 74 of FIG. 2 are to be performed as described supra inconjunction with the first dielectric material embodiment.

Joining Layer Embodiment

FIGS. 13-25 illustrate using a LCP dielectric layer as a joining layerthat mechanically and electrically joins two 2S1P substructurestogether, in accordance with embodiments of the present invention. A2S1P substructure comprises a dielectric layer having one power planewithin the dielectric layer, and two signal planes on opposing surfacesof the dielectric layer. FIGS. 13-19 depict forming a 2S1P substructure.A power plane is characterized by its inclusion of a continuouslyconductive layer and may include one or more holes within the continuousconductive layer. A signal plane is characterized by its inclusion of alayer comprising electrically conductive circuitry. FIGS. 20-23 depictforming the joining layer. FIGS. 24-25 depict joining two 2S1Psubstructures with a joining layer.

Using a LCP dielectric layer as a joining layer, rather than using aRogers 2800 dielectric material (or a partially cured thermosetmaterial) as a joining layer, has several advantages. A first advantageis that the LCP dielectric can be purchased in a copper clad format.This eliminates the need for a first step of laminating copper foil to adielectric layer. A second advantage is that the LCP dielectric is morestable and tear resistant than is the Rogers 2800 dielectric and canthus be handled in thinner sheets. This avoids the use of extra thickcopper for a central power plane, so that there is enhancement ofsubtractive circuitization and subsequent filling of fine features.

FIGS. 13-19 depict forming a 2S1P substructure 530. FIG. 13 depicts anelectrical structure 500 comprising metal layers 504 and 506 cladded toopposite sides of a dielectric layer 502. The metal layers 504 and 506may include, inter alia, copper. The dielectric layer 502 may compriseany type of dielectric material known to one of ordinary skill in theart (e.g., organic dielectric material; ceramic dielectric material; LCPdielectric material; non-LCP dielectric material; etc.). Depending onthe materials of the dielectric layer 502 and metal layers 504, it maybe possible to purchase the electrical structure 500 of FIG. 13 (e.g.,copper cladded LCP dielectric material). If the dielectric layer 502comprises LCP dielectric material then one can laminate sheets of metal(e.g., copper) to the dielectric layer 502 by the methods disclosedsupra in conjunction with the second dielectric material embodiment asdescribed supra. Otherwise, the electrical structure 500 may be formedby any method known to one of ordinary skill in the art.

FIG. 14 shows the electrical structure 500 of FIG. 13 after clearanceholes 507 and 508 have been formed in the metal layer 506, by any methodknown to one of ordinary skill in the art (e.g., patterning withphotolithography followed by chemical etching).

FIG. 15 shows the electrical structure 500 of FIG. 14 after a dielectriclayer 512 has been placed on the metal layer 506, and a metal layer 514has been placed on the dielectric layer 512. The dielectric layer 512may have any of the characteristics described supra for the dielectriclayer 502. The metal layer 514 may have any of the characteristicsdescribed supra for the metal layers 504 and 506.

FIG. 16 shows the electrical structure 500 of FIG. 15 after layers 514,512, 506, and 502 have been laminated together by any of the methodsdiscussed supra in conjunction with forming the electrical structure 500of FIG. 13, including the methods disclosed supra in conjunction withthe second dielectric material embodiment if the dielectric layer 512comprises LCP dielectric material. FIG. 16 shows that said laminationprocess caused the clearance holes 507 and 508 of FIG. 15 to be filledwith the dielectric material from dielectric layers 502 and 512.

FIG. 17 shows the electrical structure 500 of FIG. 16 after throughholes 516 and 517 have been formed through the thickness of theelectrical structure 500 in the direction 513, by any method known toone of ordinary skill in the art (e.g., laser ablation).

FIG. 18 shows the electrical structure 500 of FIG. 17 after the metallayers 504 and 514 have been removed by any method known to one ofordinary skill in the art (e.g., chemical etching), followed byformation of a blind via 518 in the dielectric layer 512 so as to exposea surface portion of the metal layer 506, by any method known to one ofordinary skill in the art (e.g., patterning with photolithographyfollowed by chemical etching).

FIG. 19 shows the result of the final step of the transformation ofelectrical structure 500 into a 2S1P substructure 530, wherein saidfinal step includes formation of plated through hole 522, plated throughhole 526, plated blind via 528, signal plane 531, and signal plane 532,by any method known to one of ordinary skill in the art such aselectroplating or electroless plating of metal (e.g., copper). Forexample: plating 520 may be plated on the walls of the through hole 516to form the plated through hole 522; plating 524 may be plated on thewalls of the through hole 517 to form the plated through hole 526;plating 527 may be plated on the walls of the blind via 518 to form theplated blind via 528; plating 501 may be plated on the surface 525 ofthe dielectric layer 512, said plating 501 being continuous with theplating 520, the plating 524, and the plating 527 to form the signalplane 531; and plating 503 may be plated on the surface 529 of thedielectric layer 502, said plating 503 being continuous with the plating520 and the plating 524 to form the signal plane 532.

The 2S1P substructure 530 comprises: the signal plane 531 on the surface525 of the dielectric layer comprising dielectric layers 512 and 502,the signal plane 532 on the surface 529 of the dielectric layercomprising dielectric layers 512 and 502, and a power plane consistingof the metal layer 506 within the dielectric layer comprising dielectriclayers 512 and 502.

FIGS. 20-23 depict forming a joining layer 559. In FIG. 20, a metal foil536 having through holes 537 and 538 is provided.

FIG. 21 is derived from FIG. 20 and shows an electrical structure 540resulting from placing LCP dielectric layers 541 and 543 on oppositesides of the metal foil 536, placing metal layer 542 on the LCPdielectric layer 541, and placing metal layer 544 on the dielectriclayer 543. The metal layers 542 and 544 may each have any of thecharacteristics described supra for the metal layers 504 and 506 of FIG.13.

FIG. 22 shows the electrical structure 540 of FIG. 21 after layers 544,543, 536, 541, and 542 have been laminated together by any of themethods discussed supra in conjunction with the second dielectricmaterial embodiment for bonding LCP material to adjacent layers. Inparticular, the lamination temperature T is to be wholly in the liquidcrystal temperature range (i.e., T<T_(NI)) of the LCP dielectricmaterial of dielectric layers 541 and 543 with no excursion into theisotropic temperature range, under sufficient pressurization (e.g., 1000to 3000 psi) and for a sufficient dwell time to cause the LCP dielectricmaterial of dielectric layers 541 and 543 to be effectively laminatedtogether in the through holes 537 and 538, and to the metal foil 536.The dwell time for maximum temperature and pressure should generally beat least 2 minutes, and applicable ranges of dwell times include, interalia, 2 to 60 minutes and 15 to 30 minutes. FIG. 22 shows that saidlamination process caused the through holes 537 and 538 of FIG. 21 to befilled with the LCP dielectric material of dielectric layers 541 and543. Following said lamination, through holes 551, 552, and 553 areformed through the thickness of the electrical structure 540 in thedirection 548.

Alternatively in FIG. 22, layer structure 546 (which includes metallayer 544, LCP dielectric layer 543, and metal foil 536), may be formedfrom a copper clad LCP core, and formed into electrical structure 540 byadding LCP dielectric layer 541 and metal layer 542.

FIG. 23 shows the result of the final step of the transformation ofelectrical structure 540 into the joining layer 559, wherein said finalstep includes forming electrically conductive plugs 555, 556, and 557within, and extending beyond in the direction 548, the through holes551, 552, and 553, respectively, by any method known to one of ordinaryskill in the art, such as by forcing electrically conductive adhesiveinto the through holes 551, 552, and 553 through use of a squeegeeprocess. The electrically conductive adhesive may comprise an adhesiveresin (e.g., epoxy) that contains conductive metal particles. As anexample, the electrically conductive adhesive may comprise AblestickABLEBOND® 8175 silver-filled paste. The adhesive is squeegeed into thethrough holes 551, 552, and 553 and smeared onto the continuing exposedsurfaces of the metal layers 542 and 544. The adhesive is partiallycured (e.g., B-stage cured). The excess partially cured adhesive is nextremoved, followed by removal of the metal layers 542 and 544 by anymethod known to one of ordinary skill in the art (e.g., chemicaletching), leaving the remaining adhesive extending above and belowdielectric layers 541 and 543 in the direction 548. The partially curedadhesive has a consistency of chewing gum at room temperature (i.e., notsticking). Then enough heat is applied to additionally cure and dry theadhesive, leaving the adhesive dry at room temperature.

As an alternative, the sidewalls of through holes 551-553 of FIG. 22could first be plated with metal (e.g., copper), followed by depositinga surface metal (e.g., tin-gold alloy) that would facilitate bonding tothe opposing or aligning plated through hole above and/or below thethrough holes 551-553. Then the electrically conductive adhesive wouldbe forced into the plated through holes 551-553 to form the electricallyconductive plugs 555-557 of FIG. 23.

FIGS. 24-25 depict joining two 2S1P substructures 560 and 570 joinedtogether mechanically and electrically by a joining layer 580 to form acomposite electrical structure 590.

FIG. 24 shows the 2S1P substructures 560 and 570 and the joining layer580 prior to the lamination process. The 2S1P substructure 560 comprisessignal planes 567 and 568 on opposing surfaces of dielectric layer 562,power plane 561 within dielectric layer 562, plated through holes 563and 564 through the thickness of the 2S1P substructure 560 in thedirection 569, and plated blind via 565 extending into the dielectriclayer 562 and mechanically and electrically contacting the power plane561. The 2S1P substructure 570 comprises signal planes 577 and 578 onopposing surfaces of dielectric layer 572, power plane 571 withindielectric layer 572, plated through holes 573 and 574 through thethickness of the 2S1P substructure 570 in the direction 569, and platedblind via 575 extending into the dielectric layer 572 and mechanicallyand electrically contacting the power plane 571. The dielectric layers562 and 572 may each independently comprise any type of dielectricmaterial known to one of ordinary skill in the art (e.g., organicdielectric material; ceramic dielectric material; LCP dielectricmaterial; non-LCP dielectric material; etc.). The joining layer 580comprises a LCP dielectric layer 582, a metal layer 581 within the LCPdielectric layer 582, and electrically conductive plugs 583, 584, and585 extending through and beyond the thickness of the joining layer 580in the direction 569.

FIG. 25 depicts the resulting composite electrical structure 590 afterthe 2S1P substructures 560 and 570 have been joined together,mechanically and electrically, by having been each laminated to thejoining layer 580. The lamination is accomplished in accordance with themethods of the second dielectric material embodiment for LCPdielectrics, described supra. In particular, the lamination temperatureT is to be wholly in the liquid crystal temperature range (i.e.,T<T_(NI)) of the LCP dielectric material of dielectric layer 582 with noexcursion into the isotropic temperature range, under sufficientpressurization (e.g., 1000 to 3000 psi) and for a sufficient dwell timeto cause the LCP dielectric material of dielectric layer 582 to beeffectively laminated to the dielectric layer 562, the dielectric layer572, the signal plane 568, and the signal plane 577. The dwell time formaximum temperature and pressure should generally be at least 2 minutes,and applicable ranges of dwell times include, inter alia, 2 to 60minutes and 15 to 30 minutes. If either or both of the dielectric layers562 and 572 comprise LCP dielectric material, then the value of T_(NI)to be employed for satisfying T<T_(NI) is the lowest value of T_(NI) ofall LCP dielectric materials included within dielectric layers 562, 572,and 582.

FIG. 25 shows that: electrically conductive plug 583 electricallycouples plated through hole 563 of the 2S1P substructure 560 to platedthrough hole 573 of the 2S1P substructure 570; electrically conductiveplug 584 electrically couples plated through hole 564 of the 2S1Psubstructure 560 to plated through hole 574 of the 2S1P substructure570; and electrically conductive plug 585 electrically couples platedblind via 565 of the 2S1P substructure 560 to plated blind via 575 ofthe 2S1P substructure 570. Additionally if the plated blind via 575 werereplaced by a new plated through hole that does not contact any portionof the metal layer 571, then the conductive plug 585 would electricallycouple plated blind via 565 of the 2S1P substructure 570 to said newplated through hole.

Any of the laminations involving LCP dielectric material describedherein in conjunction with the joining layer embodiment of the presentinvention may be performed by use of the flat bed lamination press orthe autoclave lamination press as described supra in conjunction withthe second dielectric material embodiment, or by use of any otherlamination press hardware known to one of ordinary skill in the art thatmay be used for accomplishing such laminations.

While there have been shown and described what are at present consideredthe preferred embodiments of this invention, it will be obvious to thoseskilled in the art that various changes and modifications can be madetherein without departing from the scope of the invention as defined bythe appended claims.

1. A method for forming an electrical structure, comprising: providing afirst 2S1P substructure, said first 2S1P substructure comprising a firstdielectric layer, a first power plane within the first dielectric layer,a top signal plane on a top surface of the first dielectric layer, abottom signal plane on a bottom surface of the first dielectric layer,and a first electrically conductive via; providing a second 2S1Psubstructure, said second 2S1P substructure comprising a seconddielectric layer, a second power plane within the second dielectriclayer, a top signal plane on a top surface of the second dielectriclayer, a bottom signal plane on a bottom surface of the seconddielectric layer, and a second electrically conductive via; providing ajoining layer, said joining layer having first and second opposingsurfaces and an electrically conductive plug therethrough, wherein thejoining layer comprises a liquid crystal polymer (LCP) dielectricmaterial; and directly bonding the joining layer to the first dielectriclayer of the first 2S1P substructure at the first opposing surface andto the second dielectric layer of the second 2S1P substructure at thesecond opposing surface, by subjecting the first 2S1P substructure, thejoining layer, and the second 2S1P substructure to an elevatedtemperature, elevated pressure, and dwell time sufficient foreffectuating said bonding, wherein the elevated temperature is less thanthe nematic-to-isotropic temperature of the LCP dielectric materialduring the dwell time, wherein no extrinsic adhesive material isdisposed between the joining layer and the first dielectric layer,wherein no extrinsic adhesive material is disposed between the joininglayer and the second dielectric layer, and wherein the electricallyconductive plug electrically couples the first electrically conductivevia to the second electrically conductive via.
 2. The method of claim 1,wherein the polymer chain structure and associated directionalorientation of the LCP dielectric material of the joiner layer remainsessentially unchanged throughout the dwell time.
 3. The method of claim1, wherein the coefficient of thermal expansion (CTE) of the LCPdielectric material of the joiner layer remains essentially unchangedthroughout the dwell time.
 4. The method of claim 1, wherein theelevated pressure is in a range of about 1000 psi to about 3000 psi. 5.The method of claim 4, wherein the dwell time is at least about 2minutes.
 6. The method of claim 4, wherein the first electricallyconductive via comprises a first plated through hole that electricallycouples the top and bottom signal planes of the first 2S1P substructure,and wherein the second electrically conductive via comprises a secondplated through hole that electrically couples the top and bottom signalplanes of the second 2S1P substructure.
 7. The method of claim 1,wherein the first electrically conductive via comprises a first platedblind via that electrically couples the first power plane to the bottomsignal plane of the first 2S1P substructure, and wherein the secondelectrically conductive via comprises a second plated blind via thatelectrically couples the second power plane to the top signal plane ofthe second 2S1P substructure.
 8. The method of claim 1, wherein thefirst electrically conductive via comprises a plated blind via thatelectrically couples the first power plane to the bottom signal plane ofthe first 2S1P substructure, and wherein the second electricallyconductive via comprises a plated through hole that electrically couplesthe top and bottom signal planes of the second 2S1P substructure.